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b16db81719
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51842 Commits

Author SHA1 Message Date
Evan Cheng
b16db81719 Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146805 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:25:34 +00:00
Pete Cooper
2e33944c10 Refactor code used in InstCombine::FoldAndOfICmps to new file. 
This will be used by SimplifyCfg in a later commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146803 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:20:32 +00:00
Rafael Espindola
8f7d12ccfd Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the 
asm parsing and testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:14:52 +00:00
Lang Hames
8b99c1e42c Make sure that the lower bits on the VSELECT condition are properly set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146800 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:08:46 +00:00
Jakob Stoklund Olesen
2027379985 Preserve more memory operands in ARMExpandPseudo. 
I don't think this affects anything but verbose assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146787 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 00:07:02 +00:00
Dan Gohman
ce16339930 The powers that be have decided that LLVM IR should now support 16-bit 
"half precision" floating-point with a first-class type.

This patch adds basic IR support (but not codegen support).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146786 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 00:04:22 +00:00
Eric Christopher
2e1b0c0cd9 When recursing for the original size of a type, stop if we are at a 
pointer or a reference type - we actually just want the size of the
pointer then for that.

Fixes rdar://10335756

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146785 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 23:42:45 +00:00
Eric Christopher
1a8e8869ca Resolve part of a fixme and add a new one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146784 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 23:42:42 +00:00
Eric Christopher
44625f91c5 Add a fixme here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146783 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 23:42:38 +00:00
Eric Christopher
abbb200feb Extraneous whitespace and 80-col. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146780 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 23:42:31 +00:00
Jakob Stoklund Olesen
b076fb7762 Fix off-by-one error in bucket sort. 
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.

<rdar://problem/10594653>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146767 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 23:00:05 +00:00
Dylan Noblesmith
efb0d1e42f APInt: update asserts for base-36 
Hexatridecimal was added in r139695.

And fix the unittest that now triggers the assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 20:36:31 +00:00
Jakob Stoklund Olesen
f9aabb8f32 Don't adjust for alignment padding in OffsetIsInRange. 
This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.

When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146751 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 19:10:00 +00:00
Benjamin Kramer
903456245b Hexagon: Fix a nasty order-of-initialization bug. 
Reenable the tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146750 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 19:08:59 +00:00
Devang Patel
c104cf2002 In DICompositeType, referenced to derived type is either metadata or null. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146744 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 17:51:31 +00:00
Jakob Stoklund Olesen
f5bb45f895 Note ARM constant island alignment in the release notes. 
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 16:07:41 +00:00
Manuel Klimek
76f13017fc Adds a JSON parser and a benchmark (json-bench) to catch performance regressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146735 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 13:09:10 +00:00
Chris Lattner
9646acfccf By popular demand, link up types by name if they are isomorphic and one is an 
autorenamed version of the other.   This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large app.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146728 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 08:36:07 +00:00
Craig Topper
94438ba538 Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 08:06:31 +00:00
NAKAMURA Takumi
46209476e7 Target/Hexagon: Fix CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146724 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 06:21:02 +00:00
Andrew Trick
1da282764a Avoid a confusing assert for silly options: -unroll-runtime -unroll-count=1. 
No need for an explicit test case for an unsupported combination of options.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146721 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 02:03:48 +00:00
Jim Grosbach
ddecfe54a3 ARM NEON aliases for vmovq.f* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146714 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 00:12:22 +00:00
Jim Grosbach
b6744db06f Thumb2 ADR assembly parsing w/o the .w suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146710 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 23:52:17 +00:00
Eli Friedman
7e840efc23 Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 23:46:18 +00:00
Nick Lewycky
028700f544 Move parts of lib/Target that use CodeGen into lib/CodeGen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146702 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:58:58 +00:00
Eli Friedman
2f21e8c5ba Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146700 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:56:53 +00:00
Jim Grosbach
a738da7bd3 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:56:33 +00:00
Kostya Serebryany
a4b2b1d8fb [asan] add the name of the module to the description of a global variable. This improves the readability of global-buffer-overflow reports. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146698 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:55:55 +00:00
Tony Linthicum
d239ff67f2 Add MCTargetDesc library to Hexagon target 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146692 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:29:08 +00:00
Jim Grosbach
60d99a5278 ARM NEON VTBL/VTBX assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:27:11 +00:00
Jakob Stoklund Olesen
b6ff6ec85e Enable proper constant island alignment by default. 
The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146690 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:14:45 +00:00
Chad Rosier
c8dd20170e Add missing zmovl AVX patterns which were causing crashes. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:11:31 +00:00
Kostya Serebryany
7bcfc9950b [asan] fix a bug (issue 19) where dlclose and the following mmap caused a false positive. compiler part. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146688 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 21:59:03 +00:00
Jim Grosbach
276ed0344c Silence warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146686 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 21:54:55 +00:00
Jim Grosbach
0aaf4cd9b3 ARM NEON two-register double spaced register list parsing support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146685 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 21:44:33 +00:00
Chad Rosier
0660cfe3c8 Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146684 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 21:34:44 +00:00
Lang Hames
a0a251372f Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146671 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 18:57:27 +00:00
Devang Patel
0508d047fe Update DebugLoc while merging nodes at -O0. 
Patch by Kyriakos Georgiou!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146670 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 18:21:18 +00:00
Devang Patel
9642c57ac5 Virtual table holder field is either metadata or null. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146665 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 17:55:56 +00:00
Hal Finkel
7f370b6155 Ensure that the nop that should follow a bl call in PPC64 ELF actually does 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146664 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 17:54:01 +00:00
Richard Osborne
27a7859bf7 Pass optLevel to XCoreDAGToDAGISel. 
Patch by Kyriakos Georgiou.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146656 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 15:18:35 +00:00
Eli Friedman
adeb0a6e64 Make constant folding for GEPs a bit more aggressive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146639 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 04:33:48 +00:00
Eli Friedman
ca072a3977 Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146630 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 02:07:20 +00:00
Chad Rosier
01d426e0e1 Use SmallVector/assign(), rather than std::vector/push_back(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146627 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 01:16:09 +00:00
Chad Rosier
a860b189e4 Add support for lowering fneg when AVX is enabled. 
rdar://10566486


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 01:02:25 +00:00
Pete Cooper
4e5a1ab10b Added InstCombine for "select cond, ~cond, x" type patterns 
These can be reduced to "~cond & x" or "~cond | x"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146624 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 00:56:45 +00:00
Owen Anderson
4e0adfa7f7 Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. These are already marked as illegal by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146623 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 00:54:12 +00:00
Eli Friedman
7d1ff37118 Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146621 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 00:50:34 +00:00
Bill Wendling
7a13b72bbb Re-re-enable compact unwind after fixing a failure in SingleSource/Benchmarks/Shootout-C++/except.cpp and friends. It was encoding the stored registers in the wrong order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146617 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 00:14:24 +00:00
Kevin Enderby
dac2953e3b Another improvement to the implementation of .incbin directive by avoiding a 
buffer copy.  Suggestion by Chris Lattner!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146614 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 00:00:27 +00:00