4 Commits

Author	SHA1	Message	Date
Jakob Stoklund Olesen	f06f6f50e9	Experimental support for aligned NEON spills. ... ARM targets with NEON units have access to aligned vector loads and stores that are potentially faster than unaligned operations. Add support for spilling the callee-saved NEON registers to an aligned stack area using 16-byte aligned NEON loads and store. This feature is off by default, controlled by an -align-neon-spills command line option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147211 91177308-0d34-0410-b5e6-96231b3b80d8	2011-12-23 00:36:18 +00:00
Evan Cheng	db6cbe1ff1	In Thumb2 mode, lower frame indix references to: ... add <rd>, sp, #<imm8> ldr <rd>, [sp, #<imm8>] When the offset from sp is multiple of 4 and in range of 0-1020. This saves code size by utilizing 16-bit instructions. rdar://9321541 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129971 91177308-0d34-0410-b5e6-96231b3b80d8	2011-04-22 01:42:52 +00:00
Anton Korobeynikov	57caad7a33	Preliminary support for ARM frame save directives emission via MI flags. ... This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8	2011-03-05 18:43:32 +00:00
Anton Korobeynikov	16c29b5f28	Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8	2011-01-10 12:39:04 +00:00