6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-26 21:32:10 +00:00
Code Issues Projects Releases Wiki Activity
103,805 Commits 39 Branches 0 Tags 277 MiB
b32cee560d
Commit Graph

4 Commits

Author SHA1 Message Date
Hao Liu
ae6c659d34 [ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208955 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-16 09:39:02 +00:00
Hao Liu
1c2f863df9 AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ARM64 backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208284 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-08 07:38:13 +00:00
Tim Northover
ecc1896600 AArch64/ARM64: add patterns for post-indexed ST1 ops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207840 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-02 14:54:27 +00:00
Tim Northover
6f86e23c1a AArch64/ARM64: support indexed loads/stores on vector types. 
While post-indexed LD1/ST1 instructions do exist for vector loads,
this patch makes use of the more flexible addressing-modes in LDR/STR
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207838 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-02 14:54:15 +00:00