3 Commits

Author	SHA1	Message	Date
Chris Lattner	251829ed87	eliminate some uses of prcontext. Any help here would be appreciated :) ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80520 91177308-0d34-0410-b5e6-96231b3b80d8	2009-08-30 21:45:23 +00:00
Evan Cheng	0b220d0e6c	Fix test after Chris' select changes. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66795 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-12 16:10:08 +00:00
Evan Cheng	79a796c2b1	Fix PR2536: a nasty spiller bug. If a two-address instruction uses a register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g. ... 8 %reg1024<def> = IMPLICIT_DEF 12 %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2 The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53503 91177308-0d34-0410-b5e6-96231b3b80d8	2008-07-12 01:56:02 +00:00