Commit Graph

6 Commits

Author SHA1 Message Date
Dan Gohman
e8be6c6391 Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53728 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-17 19:10:17 +00:00
Dan Gohman
95d110920e Refactor the tablegen DAGISelEmitter code for outputing calls to
getTargetNode and SelectNodeTo to reduce duplication, and to
make some of the getTargetNode code available to SelectNodeTo.
Use SelectNodeTo instead of getTargetNode in several new
interesting cases, as it mutates nodes in place instead of
creating new ones.

This triggers some scheduling behavior differences due to nodes
being presented to the scheduler in a different order. Some of the
arbitrary scheduling decisions it makes are now arbitrarily made
differently. This is visible in CodeGen/PowerPC/LargeAbsoluteAddr.ll,
where a trivial scheduling difference led to a trivial register
allocation difference.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53203 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-07 21:00:17 +00:00
Reid Spencer
c58ef0185b For PR1319: Upgrade to new test harness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36087 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-15 21:17:45 +00:00
Evan Cheng
d1b2c5b34d Fix test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34427 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-19 21:47:02 +00:00
Chris Lattner
0f74372ebf new test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34372 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-17 06:57:11 +00:00
Chris Lattner
6e1472a928 Test that large absolute addresses are properly folded into addr modes on
both ppc32 and ppc64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34370 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-17 06:41:57 +00:00