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2 Commits

Author SHA1 Message Date
Daniel Sanders
f1ef27e6e3 [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-27 10:08:31 +00:00
Daniel Sanders
a6c3a4ee76 [mips][msa] Added cfcmsa, and ctcmsa 
The MSA control registers have been added as reserved registers,
and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered
into these nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189468 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-28 10:26:24 +00:00