Commit Graph

119354 Commits

Author SHA1 Message Date
Reid Kleckner
b4eeb6bca5 [WinEH] Make sure LSDA tables are 4 byte aligned
Apparently this is important, otherwise _except_handler3 assumes that
the registration node is corrupted and ignores it.

Also fix a bug in WinEHPrepare where we would insert code after a
terminator instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241877 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 00:08:49 +00:00
Eli Bendersky
89a5e2532d Replace index-loops by range-based loops
NFC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241875 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 23:06:03 +00:00
Sanjay Patel
c68ccc1a70 [x86] enable machine combiner reassociations for scalar double-precision multiplies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241873 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:58:39 +00:00
Sanjay Patel
39f09b5150 [x86] enable machine combiner reassociations for scalar double-precision adds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241871 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:48:54 +00:00
Michael J. Spencer
478d483d7e Fix shadowing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241870 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:42:21 +00:00
Michael J. Spencer
8109763d68 [Object][ELF] Support dumping hash-tables from files with no section table.
This time without breaking the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241869 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:32:24 +00:00
Alex Lorenz
ad6702ec23 MIR Serialization: Serialize the virtual register definitions.
The virtual registers are serialized using a YAML sequence of YAML inline
mappings. Each mapping has the id of the virtual register and the register
class.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10981


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241868 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:23:13 +00:00
Adam Nemet
81e7e2dfab [LAA] Fix grammar in debug output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241867 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:17:41 +00:00
Adam Nemet
1c25d370c1 [LAA] Hide NeedRTCheck logic completely inside canCheckPtrAtRT, NFC
Currently canCheckPtrAtRT returns two flags NeedRTCheck and CanDoRT.
NeedRTCheck says whether we need checks and CanDoRT whether we can
generate the checks.  The idea is to encode three states with these:

     Need/Can:
(1) false/dont-care: no checks are needed
(2) true/false: we need checks but can't generate them
(3) true/true: we need checks and we can generate them

This is pretty unnecessary since the caller (analyzeLoop) is only
interested in whether we can generate the checks if we actually need
them (i.e. 1 or 3).

So this change cleans up to return just that (CanDoRTIfNeeded) and pulls
all the underlying logic into canCheckPtrAtRT.

By doing all this, we simplify analyzeLoop which is the complex function
in LAA.

There is further room for improvement here by using RtCheck.Need
directly rather than a new local variable NeedRTCheck but that's for a
later patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241866 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:17:38 +00:00
Reid Kleckner
5cf6c0b070 [WinEH] Give up on using CSRs across 32-bit invokes for now
The runtime does not restore CSRs when transferring control back to the
function handling the exception. According to the experts on IRC, LLVM's
register allocator has no way to model register clobbers that only
happen on one edge of the CFG. For now, don't worry about trying to use
the meager three CSRs available on 32-bit X86 and just say that such
invokes preserve nothing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241865 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:09:41 +00:00
Reid Kleckner
827f211e95 Expose sjlj preparation through opt for my own debugging purposes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241864 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:48:40 +00:00
Alex Lorenz
ccba68af82 MIR Parser: Report an error when parsing machine function with an empty body.
This commit adds a new error which is reported when the MIR Parser encounters
a machine function without any machine basic blocks. The machine verifier
expects that the machine functions have at least one MBB, and this error will
prevent machine functions without MBBs from reaching the machine verifier and
crashing with an assertion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241862 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:21:33 +00:00
Tom Stellard
847c023a2e AMDGPU: Add helper function for implicit parameter offsets.
Patch by: Zoltan Gilian

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241861 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:20:37 +00:00
JF Bastien
b5ebaf3ae5 Unbreak WebAssembly build
Summary: D11021 and D11045 didn't update the WebAssembly target's code. It's still experimental so all tests passed.

Reviewers: sunfish, joker.eph, echristo

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11084

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241859 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:00:09 +00:00
JF Bastien
51e46420ea WebAssembly: add placeholder intrinsics header
Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11080

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241858 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 20:57:38 +00:00
Sanjoy Das
efec6ccae3 [ImplicitNullChecks] Fix a memory leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241851 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 20:13:31 +00:00
Sanjoy Das
a5a3e2d58a [ImplicitNullChecks] Be smarter in picking the memory op.
Summary:
Before this change ImplicitNullChecks would only pick loads of the form:

```
   test Reg, Reg
   jz elsewhere
 fallthrough:
   movl 32(Reg), Reg2
```

but not (say)

```
   test Reg, Reg
   jz elsewhere
 fallthrough:
   inc Reg3
   movl 32(Reg), Reg2
```

This change teaches ImplicitNullChecks to look through "unrelated"
instructions like `inc Reg3` when searching for a load instruction
to convert to a trapping load.

Reviewers: atrick, JosephTremoulet, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11044

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241850 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 20:13:25 +00:00
Rafael Espindola
377796abdf Create BSD archives by default on OS X.
They should probably be created on anything that is not windows or linux, but I will
test on freebsd before changing that.

With this it is possible to bootstrap with llvm-ar instead of ar+ranlib on OS X.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241849 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 20:12:50 +00:00
Alex Lorenz
7c6ad33126 MIR Serialization: Serialize the simple MachineFrameInfo attributes.
This commit serializes the 13 scalar boolean and integer attributes from the
MachineFrameInfo class: IsFrameAddressTaken, IsReturnAddressTaken, HasStackMap,
HasPatchPoint, StackSize, OffsetAdjustment, MaxAlignment, AdjustsStack,
HasCalls, MaxCallFrameSize, HasOpaqueSPAdjustment, HasVAStart, and
HasMustTailInVarArgFunc. These attributes are serialized as part
of the frameInfo YAML mapping, which itself is a part of the machine function's
YAML mapping.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241844 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 19:55:27 +00:00
Rafael Espindola
7255090cd3 llvm-ar: Pad the symbol table to 4 bytes.
It looks like ld64 requires it. With this we seem to be able to bootstrap using
llvm-ar+/usr/bin/true instead of ar+ranlib (currently on stage2).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241842 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 19:48:06 +00:00
Matt Arsenault
0685a5c5ed AMDGPU/R600: Return correct chain when lowering loads
The other LowerLOAD should be returning the correct chain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241839 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:47:03 +00:00
Sanjoy Das
4db527032a [IndVars] Try to use existing values in RewriteLoopExitValues.
Summary:
In RewriteLoopExitValues, before expanding out an SCEV expression using
SCEVExpander, try to see if an existing LLVM IR expression already
computes the value we're interested in.  If so use that existing
expression.

Apart from reducing IndVars' reliance on the rest of the compilation
pipeline, this also prevents IndVars from concluding some expressions as
"high cost" when they're not.  For instance,
`InductiveRangeCheckElimination` often emits code of the following form:

```
len = umin(len_A, len_B)

loop:
  ...
  if (i++ < len)
    goto loop

outside_loop:
    use(i)
```

`SCEVExpander` refuses to rewrite the use of `i` in `outside_loop`,
since it thinks the value of `i` on loop exit, `len`, is a high cost
expansion since it contains an `umax` in it.  With this change,
`IndVars` can see that it can re-use `len` instead of creating a new
expression to compute `umin(len_A, len_B)`.

I considered putting this cleverness in `SCEVExpander`, but I was
worried that it may then have a deterimental effect on other passes
that use it.  So I decided it was better to just do this in the one
place where it seems like an obviously good idea, with the intent of
generalizing later if needed.

Reviewers: atrick, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10782

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241838 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:46:12 +00:00
Simon Atanasyan
13c5e09c6e [llvm-readobj] Print MIPS PLT table
Now the -mips-plt-got prints both MIPS GOT and PLT tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241836 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:23:10 +00:00
Simon Atanasyan
ba8d948e93 [yaml2obj] Initialize sh_addralign field for the .symtab section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241835 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:23:02 +00:00
Simon Atanasyan
085d10b151 [ELF] Explicitly configure sections alignment in the tests. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241834 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:22:55 +00:00
David Majnemer
8343a0aa3b [llvm-readobj] Re-add sanity checking which was accidentally removed in r241764
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241831 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:14:31 +00:00
David Majnemer
f2c71ff7a8 [llvm-objdump] Require that jump targets shown in -d are functions
Don't let the disassembler pick call <.text> if a function happens to
live at the start of the section by only using function symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241830 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:11:40 +00:00
Reid Kleckner
5574399e37 Remove dead code from old 64-bit SEH lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241829 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:46:39 +00:00
Pat Gavlin
db5a82b861 Allow {e,r}bp as the target of {read,write}_register.
This patch allows the read_register and write_register intrinsics to
read/write the RBP/EBP registers on X86 iff the targeted register is
the frame pointer for the containing function.

Differential Revision: http://reviews.llvm.org/D10977

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241827 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:40:29 +00:00
Sanjay Patel
dc219dddde fix an invisible bug when combining repeated FP divisors
This patch fixes bugs that were exposed by the addition of fast-math-flags in the DAG:
r237046 ( http://reviews.llvm.org/rL237046 ):

1. When replacing a division node, it's not enough to RAUW.
   We should call CombineTo() to delete dead nodes and combine again.
2. Because we are changing the DAG, we can't return an empty SDValue
   after the transform. As the code comments say:

    Visitation implementation - Implement dag node combining for different node types.
    The semantics are as follows: Return Value:
      SDValue.getNode() == 0 - No change was made
      SDValue.getNode() == N - N was replaced, is dead and has been handled.
      otherwise - N should be replaced by the returned Operand.

The new test case shows no difference with or without this patch, but it will crash if
we re-apply r237046 or enable FMF via the current -enable-fmf-dag cl::opt.

Differential Revision: http://reviews.llvm.org/D9893



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241826 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:28:37 +00:00
Juergen Ributzka
c014920a89 [StackMap] Use lambdas to specify the sort and erase conditions. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241823 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:11:15 +00:00
Juergen Ributzka
fd5ef9d20c [StackMap] Rename variables to be more consistent. NFC.
Rename a few variables and use auto for long iterator names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241822 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:11:11 +00:00
Juergen Ributzka
9ba87b84ab [StackMaps] Use emplace_back when possible. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241821 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:11:08 +00:00
Silviu Baranga
c0970bdc63 Add a test of a regression discovered during testing of r241673
Summary:
We were missing a corner case where DepCands was not available,
but we were using DepCands to compute the checking pointer
groups.

This adds a test for that regression.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11068

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241818 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 16:40:25 +00:00
Tom Stellard
2b2d86178c AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with one use
This is convered by existing testcases and will be exposed by a future
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241817 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 16:30:36 +00:00
Tom Stellard
e05910e677 AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()
No test case for this.  I ran into it while working on some improvements
to SIShrinkInstructions.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241816 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 16:30:27 +00:00
Rafael Espindola
c9799867af Add missing file from previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241815 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:58:22 +00:00
Rafael Espindola
a55816b3fc Basic support for BSD symbol tables in archives.
This could be optimized and for now we only produce __.SYMDEF
and not "__.SYMDEF SORTED".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241814 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:56:23 +00:00
Krzysztof Parzyszek
8e78dfcf23 [Hexagon] Add missing preamble to a source file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241813 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:40:25 +00:00
Rafael Espindola
f336caf392 Remove redundant variable. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241810 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:24:39 +00:00
Silviu Baranga
f283cd9acf Don't rely on the DepCands iteration order when constructing checking pointer groups
Summary:
The checking pointer group construction algorithm relied on the iteration on DepCands.
We would need the same leaders across runs and the same iteration order over the underlying std::set for determinism.

This changes the algorithm to process the pointers in the order in which they were added to the runtime check, which is deterministic.
We need to update the tests, since the order in which pointers appear has changed.

No new tests were added, since it is impossible to test for non-determinism.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11064

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241809 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:18:25 +00:00
Rafael Espindola
3696927846 Add a helper to printing BE of LE depending on the format.
The gnu ar format uses BE numbers. The BSD one uses LE. Add a helper for one or the
other. NFC for now, just removes some noise from the following patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241808 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:13:41 +00:00
Mehdi Amini
cdc323b2b7 Re-instate the EVT parameter to getScalarShiftAmountTy() for OOT user
A documentation for this function would be nice by the way.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241807 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:12:23 +00:00
Pawel Bylica
dbbfabaf01 Reapply fixed r241790: Fix shift legalization and lowering for big constants.
Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt.

Reviewers: nadav, majnemer, sanjoy, RKSimon

Subscribers: RKSimon, llvm-commits

Differential Revision: http://reviews.llvm.org/D10767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241806 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:58:04 +00:00
Rafael Espindola
56240eaf73 Extract printBSDMemberHeader.
It will get another use in the following patch. Also rename the other helper to
printGNUSmallMemberHeader for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241805 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:54:12 +00:00
Krzysztof Parzyszek
b13f72aa2d [Hexagon] Add support for atomic RMW operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241804 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:51:21 +00:00
Arnaud A. de Grandmaison
86d3dfce62 [AArch64] Select SBFIZ or UBFIZ instead of left + right shifts
And rename LSB to Immr / MSB to Imms to match the ARM ARM terminology.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241803 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:33:38 +00:00
Scott Douglass
0e714c7efa [ARM] Thumb1 3 to 2 operand convertion for commutative operations
Differential Revision: http://reviews.llvm.org/D11057

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241802 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:13:55 +00:00
Scott Douglass
7b8defda79 [ARM] Don't be overzealous converting Thumb1 3 to 2 operands
Differential Revision: http://reviews.llvm.org/D11056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241801 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:13:48 +00:00
Scott Douglass
3ca1884ba8 [ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2
Differential Revision: http://reviews.llvm.org/D11055

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241800 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:13:41 +00:00