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13719 Commits

Author SHA1 Message Date
Daniel Dunbar
a8dfb79e6f X86: Move extended MCFixupKinds into X86FixupKinds.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96088 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 09:27:52 +00:00
Chris Lattner
b779033a23 add encoder support and tests for rdtscp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96076 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 03:42:24 +00:00
Johnny Chen
a1e7621510 Add SETEND and BXJ instructions for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96075 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 02:51:09 +00:00
Sean Callanan
cebe955779 Added the rdtscp instruction to the x86 instruction 
tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96073 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 02:06:11 +00:00
Evan Cheng
7545f49a5e Teach MachineFrameInfo to track maximum alignment while stack objects are being 
created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96069 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 01:56:41 +00:00
Sean Callanan
95a5a7d570 Fixed encodings for invlpg, invept, and invvpid. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96065 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 01:48:34 +00:00
Johnny Chen
08b85f371e Added a bunch of saturating add/subtract instructions for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96063 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 01:21:01 +00:00
Chris Lattner
f068304b1f rip out the 'heinous' x86 MCCodeEmitter implementation. 
We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96059 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 00:49:29 +00:00
Chris Lattner
a599de2410 remove special cases for vmlaunch, vmresume, vmxoff, and swapgs 
fix swapgs to be spelled right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 00:41:14 +00:00
Daniel Dunbar
9c60f534cb MC/X86: Push immediate operands as immediates not expressions when possible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96055 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 00:17:21 +00:00
Chris Lattner
eaca5fa8e6 Remove special cases for [LM]FENCE, MONITOR and MWAIT from 
encoder and decoder by using new MRM_ forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96048 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 23:54:57 +00:00
Chris Lattner
4a2e5edb94 implement the rest of correct x86-64 encoder support for 
rip-relative addresses, and add a testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96040 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 23:24:09 +00:00
Dale Johannesen
15ce1d71f1 Add the problem I just hacked around in 96015/96020. 
The solution there produces correct code, but is seriously
deficient in several ways.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 23:16:24 +00:00
Chris Lattner
86020e4628 give MCCodeEmitters access to the current MCContext. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96038 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 23:12:47 +00:00
Chris Lattner
835acabce1 implement infrastructure to support fixups for rip-rel 
addressing.  This isn't complete because I need an MCContext
to generate new MCExprs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96036 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 23:00:36 +00:00
Johnny Chen
f4d81051ff Add YIELD, WFE, WFI, and SEV instructions for disassembly only. 
Plus add two formats: MiscFrm and ThumbMiscFrm.  Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96032 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 22:53:19 +00:00
Chris Lattner
1e35d0e923 pull the rip-relative addressing mode case up early. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 22:47:55 +00:00
Chris Lattner
9cc48eb897 fixme resolved! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96029 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 22:39:06 +00:00
Chris Lattner
cf65339b52 start producing reloc_pcrel_4byte/reloc_pcrel_1byte for calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96028 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 22:36:47 +00:00
Chris Lattner
a0331199fc enhance the immediate field encoding to know whether the immediate 
is pc relative or not, mark call and branches as pcrel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96026 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 22:27:07 +00:00
Evan Cheng
3f7aa79c2a Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96023 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 22:17:21 +00:00
Dale Johannesen
ee25bc2942 This should have gone in with 26015, see comments there. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96020 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 22:00:40 +00:00
Johnny Chen
83498e55e2 Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96019 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 21:59:23 +00:00
Dale Johannesen
c12da8d30a When save/restoring CR at prolog/epilog, in a large 
stack frame, the prolog/epilog code was using the same
register for the copy of CR and the address of the save slot.  Oops.
This is fixed here for Darwin, sort of, by reserving R2 for this case.
A better way would be to do the store before the decrement of SP,
which is safe on Darwin due to the red zone.

SVR4 probably has the same problem, but I don't know how to fix it;
there is no red zone and R2 is already used for something else.
I'm going to leave it to someone interested in that target.

Better still would be to rewrite the CR-saving code completely;
spilling each CR subregister individually is horrible code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96015 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 21:35:34 +00:00
Chris Lattner
fdfeb6976f Add support for a union type in LLVM IR. Patch by Talin! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96011 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 20:49:41 +00:00
Johnny Chen
b3e1bf54b2 Add SWP (Swap) and SWPB (Swap Byte) for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96010 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 20:48:24 +00:00
Johnny Chen
b98e160318 Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95999 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 18:55:33 +00:00
Anton Korobeynikov
ebb0c2b287 Setup correct data layout to match gcc's expectations on mingw32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95981 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 15:28:56 +00:00
Anton Korobeynikov
4dd162f394 Cleanup stdcall / fastcall name mangling. 
This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95980 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 15:28:40 +00:00
Chris Lattner
0d8db8e0a8 add a bunch of mod/rm encoding types for fixed mod/rm bytes. 
This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95960 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 02:06:33 +00:00
Chris Lattner
c96f6d606f revert r95949, it turns out that adding new prefixes is not a 
great solution for the disassembler, we'll go with "plan b".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95957 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 01:55:31 +00:00
Johnny Chen
906d57ffe8 Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, 
MRRC, MRRc2.  For disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 01:44:23 +00:00
Daniel Dunbar
ccfa1db538 X86: Fix definition for RCL/RCR.*m? operations -- they were getting represented 
with "tied memory operands", which is wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 01:22:03 +00:00
Chris Lattner
239a1edbab add another bit of space for new kinds of instruction prefixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95949 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 01:15:16 +00:00
Nate Begeman
7cdba6d1f4 Add a missing pattern for movhps so that we get: 
movq	(%ecx,%edx,2), %xmm2
movhps	(%ecx,%eax,2), %xmm2

rather than:

movq     (%eax, %edx, 2), %xmm2		
movq     (%eax, %ebx, 2), %xmm3		
movlhps  %xmm3, %xmm2			

Testcase forthcoming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95948 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 01:10:45 +00:00
Chris Lattner
c4d3f662fc fix the encodings of monitor and mwait, which were completely 
busted in both encoders.  I'm not bothering to fix it in the
old one at this point.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 01:06:22 +00:00
Chris Lattner
0d7b0aa760 enhance llvm-mc -show-inst to print the enum of an instruction, like so: 
testb	%al, %al                ## <MCInst #2412 TEST8rr
                                        ##   <MCOperand Reg:2>
                                        ##   <MCOperand Reg:2>>
	jne	LBB1_7                  ## <MCInst #938 JNE_1
                                        ##   <MCOperand Expr:(LBB1_7)>>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95935 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 22:57:32 +00:00
Chris Lattner
7e85180d15 add a new MCInstPrinter::getOpcodeName interface, when it is 
implemented, llvm-mc --show-inst now uses it to print the
instruction opcode as well as the number.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95929 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 22:39:10 +00:00
Chris Lattner
b8db331588 improve encoding information for branches. We now know they have 
8 or 32-bit immediates, which allows the new encoder to handle
them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95927 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 21:45:31 +00:00
Chris Lattner
8d31de6268 make getFixupKindInfo return a const reference, allowing 
the tables to be const.  Teach MCCodeEmitter to handle
the target-indep kinds so that we don't crash on them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95924 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 21:27:18 +00:00
Chris Lattner
11eafa8bed switch to target-indep fixups for 1/2/4/8 byte data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95920 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 21:17:54 +00:00
Johnny Chen
e4c7f0f6ec Added LDRT/LDRBT/STRT/STRBT for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95916 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 20:31:08 +00:00
Chris Lattner
8b442a814e unbreak the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95915 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 19:52:11 +00:00
Chris Lattner
bd13fb6254 refactor the conditional jump instructions in the .td file to 
use a multipattern that generates both the 1-byte and 4-byte 
versions from the same defm


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95901 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 19:25:55 +00:00
Johnny Chen
811663f799 Forgot to also check in this file for vcvt (floating-point <-> fixed-point, VFP). 
Sorry!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95892 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 18:47:03 +00:00
Johnny Chen
27bb8d0a88 Added VCVT (between floating-point and fixed-point, VFP) for disassembly. 
A8.6.297


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95885 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 18:17:16 +00:00
Johnny Chen
c6f7b27fda Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95884 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 18:12:29 +00:00
Johnny Chen
ba6e033f4f Add pseudo instruction TRAP for disassembly, which is encoded according to A5-21 
as the "Permanently UNDEFINED" instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95873 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 17:14:31 +00:00
Chris Lattner
ecfb3c3d66 dont' call getX86RegNum on X86::RIP, it doesn't like that. This 
fixes the remaining x86-64 jit failures afaik.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95867 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 08:45:56 +00:00
Chris Lattner
5526b69901 fix a really nasty bug I introduced in r95693: r12 (and r12d, 
r12b, etc) also encodes to a R/M value of 4, which is just
as illegal as ESP/RSP for the non-sib version an address.

This fixes x86-64 jit miscompilations of a bunch of programs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95866 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 08:41:21 +00:00