Avoid a fall-through in the (stubby) treatment of the longjmp intrinsic
call which causes llc & lli to core-dump.
Add a sort-of treatment of cast double to ulong. I am not really sure
what a user should expect to see upon casting a negative FP value to
unsigned long long. But with what is given here, I was able to write
a program that could cast -123.456 to ulong and back and get -123.0,
which seems like a step in the right direction. GCC seems to give you
0. I don't know if I'd consider that useful.
These cases were coming up in GNU coreutils-5.0.
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to pass to dlsym() -- Linux/x86 wants 0 while Sparc/Solaris wants RTLD_SELF,
which is not zero. Thanks to Chris for the suggestion.
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an external constant. Since external constants don't have initializers, we
were failing on an assert() call in llvm/GlobalVariable.h.
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after all callees are inlined into the current graph.
NOTE: There's also a major bug fix for the BU pass in DataStructure.cpp,
which ensures that resolvable indirect calls are not moved out to the
globals graph, so that they are eventually inlined (if possible).
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after all callers are inlined into the current graph.
(2) Optimize the way a graph is inlined into its callees in the TD phase:
(a) Use DSGraph::cloneReachableSubgraph to clone only a subgraph at
each call site, for faster inlining.
(b) Clone separately for the same callee at different call sites,
since only the reachable subgraph is being cloned, not the entire
caller graph.
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and (2) faster inlining by cloning only reachable nodes. In particular:
(1) Added DSGraph::cloneReachableSubgraph and DSGraph::cloneReachableNodes
to clone the subgraph reachable from a set of root nodes, into the
current graph, merging the global nodes into thos in the current graph.
The TD pass now uses this for faster inlining, and so does the
next function.
(2) Added DSGraph::updateFromGlobalGraph() to rematerialize nodes from the
globals graph into the current graph in both BU and TD passes.
(3) `I' flags are removed from all nodes in the globals graph, because they
are difficult to maintain correctly and are not needed anyway.
(4) Aux. function calls are only removed to the globals graph if they
will never be resovled. (This is what fixed gap.) The immediate
reason is that if we took these out of a function (and moved them to
the globals graph) we would need to rematerialize these nodes into the
function graph for every function in the BU pass. The longer term
problem is that we would need to find a way to remove them from the
globals graph iff they have been resolved on all paths through the
call graph.
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isUnresolvableFunc() (I thought I needed this externally.
I don't, but it's still nicer this way.)
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now works in instructions which require a 2-bit or 3-bit INTcc code.
Incidentally, that means that the representation of INTcc registers is now the
same in both integer and FP instructions. Thus, code became much simpler and
cleaner.
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allow, i.e. make a sequence of instructions to enable an indirect call using
jump-and-link and 2 temporary registers (which we save and ultimately restore).
Warning: if the delay slot of a function call is used to do meaningful work and
not just a NOP, this behavior is incorrect. However, the Sparc backend does not
yet utilize the delay slots effectively, so it is not necessary to make an
overly complicated algorithm for something that's not used.
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* FP double registers are now coded correctly
* Removed function which converted registers based on register types, it was
broken (because regTypes are broken)
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remembered in valuesStoredInFunction, but never traced at function return,
and that's too late to be finding the error anyway).
Stores trace both the value and the address being stored to,
but after some experience I think only values should be traced.
The pointer hash table just fills up far too quickly if every
store address were traced.
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out the entire llvm disassembly for the function at global constant-output
time, which caused the assembler to barf in 164.gzip. This fixes that
particular problem (though 164.gzip has other problems with X86 llc.)
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Fhourstones, McCat-vor, and many others...)
Printer.cpp: Print implicit uses for AddRegFrm instructions. Break gas
bug workarounds up into separate stanzas of code for each bug. Add new
workarounds for fild and fistp.
X86InstrInfo.def: Add O_ST0 implicit uses for more FP instrs where they
obviously apply. Also add PrintImplUses flags for FP instrs where they
are necessary for gas to understand the output.
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(1) Cannot use ANDN(ot), ORN, and XORN for boolean ops, only bitwise ops.
(2) Conditional move instructions must distinguish signed and unsigned
condition codes, e.g., MOVLE vs. MOVLEU.
(3) Conditional-move-on-register was using the cond-move-on-cc opcodes,
which produces a valid-looking instruction with bogus registers!
(4) Here's a really cute one: dividing-by-2^k for negative numbers needs to
add 2^k-1 before shifting, not add 1 after shifting. Sadly, these
are the same when k=0 so our poor test case worked fine.
(5) Casting between signed and unsigned values was not correct:
completely reimplemented.
(6) Zero-extension on unsigned values was bogus: I was only doing the
SRL and not the SLLX before it. Don't know WHAT I was thinking!
(7) And the most important class of changes: Sign-extensions on signed values.
Signed values are not sign-extended after ordinary operations,
so they must be sign-extended before the following cases:
-- passing to an external or unknown function
-- returning from a function
-- using as operand 2 of DIV or REM
-- using as either operand of condition-code setting operation
(currently only SUBCC), with smaller than 32-bit operands
Also, a couple of improvements:
(1) Fold cast-to-bool into Not(bool). Need to do this for And, Or, XOR also.
(2) Convert SetCC-Const into a conditional-move-on-register (case 41)
if the constant is 0. This was only being done for branch-on-SetCC-Const
when the branch is folded with the SetCC-Const.
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(1) An int CC live range must be spilled if there are any interferences,
even if no other "neighbour" in the interf. graph has been allocated
that reg. yet. This is actually true of any class with only one reg!
(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
be spilled so that the machine-independent spill code doesn't have to
make the machine-dependent decision of which CC name to use based on
operand type: %xcc or %icc. (These are two halves of the same
register.)
(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
These should never have been the same, and this is necessary now for #2.
(4) All RDCCR and WRCCR instructions are directly generated with the
phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
deal with this.
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(1) An int CC live range must be spilled if there are any interferences,
even if no other "neighbour" in the interf. graph has been allocated
that reg. yet. This is actually true of any class with only one reg!
(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
be spilled so that the machine-independent spill code doesn't have to
make the machine-dependent decision of which CC name to use based on
operand type: %xcc or %icc. (These are two halves of the same register.)
(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
These should never have been the same, and this is necessary now for #2.
(4) All RDCCR and WRCCR instructions are directly generated with the
phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
deal with this.
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integer overflow):
We need to use %icc and not %xcc for comparisons on 32-bit or smaller
integer values.
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correct: empirically, "regType" is wrong for a number of registers. Thus, one
can only rely on the "regClass" to figure out what kind of register one is
dealing with.
This change switches to using only "regClass" and adds a few extra DEBUG() print
statements and a few clean-ups in comments and code, mostly minor.
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the TableGen descriptions; all unset bits are thus errors.
* As a result, found and fixed instructions where some operands were not
actually assigned into the right portion of the instruction.
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* Setting ENABLE_X86_JIT or ENABLE_SPARC_JIT on the `make' command-line will
force the inclusion of that JIT on a different architecture
* If neither JIT is enabled (e.g., compiling on a different architecture), the
-march option will not be available to LLI.
* As a side effect of the $ARCH variable, the Sparc LLI can now link just a bit
faster by not including the x86 library.
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area to avoid using up precious stack space within the 4095 offset limit
from %fp. Such objects that would themselves live at a large offset
were being put there already so this is a simple change.
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deletes it, but we were merrily trying to fix the operands of that
instruction anyway! Instead, fix the replacement instruction.
(2) An Improvement: Check for and extract global values in all operands,
not just in known pointer operands. For example, they can occur in
call arguments, and probably other unforeseeable places as well.
This also eliminates the special-case handling of Load and Store.
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not just an Instruction*, at least in one unfortunate case:
the first operand to the va_arg instruction.
Modify ValueToDefVecMap to map from Value*, not Instruction*.
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(1) select: Ok to convert a pointer to a float or double.
(2) regalloc: Some MachineInstr* for caller-saving code before a call
were being inserted before and after the call!
(3) Don't insert the caller-saving instructions in the
MachineCodeForInstruction for the Call instruction.
*All* instructions generated by register allocation need to be
recorded in those maps, but it needs to be done uniformly.
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read or written to. Keep track of how many times this happens. This should
be good for deleting things like references to type information in C++ classes
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SingleSource except oopack and Oscar. (Sorry, Oscar.)
include/llvm/Target/TargetInstrInfo.h: Remove virtual print method. Add
accessors for ImplicitUses/Defs.
lib/Target/TargetInstrInfo.cpp: Remove virtual print method. If you
really wanted this, just use MI->print(O, TM); instead...
lib/Target/X86:
FloatingPoint.cpp: ...like this.
X86InstrInfo.h: Remove virtual print method. Define the PrintImplUses
target-specific flag bit.
X86InstrInfo.def: Add the PrintImplUses flag to all the instructions
which implicitly use CL, because the assembler needs to see the CL in
order to generate the right instruction.
Printer.cpp: Ditch fnIndex at Chris's request. Now we use CurrentFnName
to name constants in the constant pool for each function instead. This
avoids keeping state between runOnMachineFunction() invocations, which
is a no-no. Having MangledGlobals be global is a bogon I'd like to get
rid of too, but making it a static member of Printer causes link errors
(why???).
Make NumberForBB into a member of Printer instead of a global, too.
Make printOp and printMemReference into methods of Printer.
X86InstrInfo::print is now Printer::printMachineInstruction, because
TargetInstrInfo::print is history. (Because of this, we have to qualify
the names of some TargetInstrInfo methods we call.)
Print out the ImplicitUses field of any instruction we print that has
the PrintImplUses bit set.
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particular, name mangling for GlobalValues only occurs when the linkage type is
internal or when the name must be mangled to avoid a collision. See comments in
CWriter::getValueName for more information.
- 'inline' keyword is now emitted for functions with 'linkonce' linkage type.
- Fixed typos.
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want to mark it live if it is an unconditional branch. This fixes bug:
ADCE/2002-05-28-Crash.ll and makes this pass _much_ more useful.
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Replace (cast (sub A, B) to bool) -> (setne A, B)
Replace (cast (add A, B) to bool) -> (setne A, -B)
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* Add new MultiObject flag to DSNode which keeps track of whether or not
multiple objects have been merged into the node, allowing must-alias info
to be tracked.
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involves removing the [bwl] suffixes from instruction names, as well
as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.)
Lowercase all instr. names as well for consistency's sake.
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to print various things on a module-by-module basis (currently, only the
former is used).
Don't print < > around names. The assembler can't take it.
Print pseudoinstructions only as comments. The poor little assembler can't
take that, either.
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Move LowerAllocations, PrintFunction, and SymbolStripping passes, and
the corresponding -disable-strip and -d options, over here to the SPARC
target-specific bits of llc. Rename -d to -dump-asm.
tools/llc/Makefile:
Reindent. Add x86 library so that llc compiles again.
tools/llc/llc.cpp:
Remove support for running arbitrary optimization passes. Use opt instead.
Remove LowerAllocations, PrintFunction, and SymbolStripping passes, as noted
above.
Allow user to select a backend (x86 or SPARC); default to guessing from
the endianness/pointer size of the input bytecode file.
Fix typos.
Delete empty .s file and exit with error status if target does not support
static compilation.
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into a new function FPCSafeToPrint(), and use it in printConstant()
and printFunction() to decide whether we should output ConstantFPs as
floating-point constants or as references to stack-allocated variables.
lib/VMCore/AsmWriter.cpp: Fix an apparent typo in the code mentioned above.
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(We're already talking about autoconf'ing this, so I'm assuming this hack
will be short-lived...I just don't want it to get lost in my working files.)
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link in the X86 JIT either, but this makes testing easier.
For some reason, the sparc JIT was breaking the X86 JIT when it was linked in. :(
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instead of a variable pointer and an alloca. All accesses to the variable then
use the address-of operator to access it. This plays better with the internal
GCC code generation phases, which bail early on functions which contain allocas.
It also makes the code a bit easier to read.
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This was because we were deleting large chunks of functions without an exit block, because the post-dominance
information was not useful. This broke crafty and twolf.
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SETTING the operand to be an immediate or have verified that one of the operands
is really a SignExtended or Unextended immediate value already, which warrants
an 'i' opcode.
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* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes
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* Removed instruction scheduling as it is too slow to run in a JIT environment
* Removed other passes because they aren't necessary and can slow JIT down
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The JIT is designed to code-generate a function at-a-time. That means that any
pass can only make local changes to its function. Period.
Because the Sparc PreSelection pass claims to be a BasicBlock pass while adding
globals to the Module, it cannot be run with the other passes, because by this
time, the globals have been output already by the JIT, and the addresses of any
globals appearing AFTER this point are not recognized.
However, the PreSelection pass is a requirement for correctness in the Sparc
codegen path, so it MUST be run.
::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT :::
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This avoid generating a register to hold C, which in turn speeds up the
register allocator by a lot: ~9% on 164.gzip and ~17% on 256.bzip2. This
also speeds up other passes. This also speeds up execution of the program
marginally, and makes the asm much easier to read. :)
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