Commit Graph

90798 Commits

Author SHA1 Message Date
Andrew Trick
bc4de7cec1 Fix TableGen subtarget-emitter to handle A9/Swift.
A9 uses itinerary classes, Swift uses RW lists. This tripped some
verification when we're expanding variants. I had to refine the
verification a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178357 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 19:08:31 +00:00
Matt Arsenault
71246fb830 Build fixes for STLPort + GCC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 18:48:45 +00:00
Matt Arsenault
7d4ff60b55 Fix loop style
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178355 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 18:48:42 +00:00
Adrian Prantl
f24caa4421 Split the llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m testcase into a CFE and LLVM part.
rdar://problem/12767564

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178353 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 18:08:14 +00:00
Benjamin Kramer
74a4533a42 Remove the old CodePlacementOpt pass.
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 17:14:24 +00:00
Nadav Rotem
975ee54731 Fix a typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178346 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 16:34:23 +00:00
Jyotsna Verma
65063feac5 Hexagon: Disable DwarfUsesInlineInfoSection flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178345 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 15:46:12 +00:00
Hal Finkel
f5d5c43460 Add PPC FP rounding instructions fri[mnpz]
These instructions are available on the P5x (and later) and on the A2. They
implement the standard floating-point rounding operations (floor, trunc, etc.).
One caveat: frin (round to nearest) does not implement "ties to even", and so
is only enabled in fast-math mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178337 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 08:57:48 +00:00
Rafael Espindola
ef484a376c Revert "Fix allocations of SmallVector and SmallPtrSet so they are more prone to"
This reverts commit 617330909f.

It broke the bots:

/home/clangbuild2/clang-ppc64-2/llvm.src/unittests/ADT/SmallVectorTest.cpp:150: PushPopTest
/home/clangbuild2/clang-ppc64-2/llvm.src/unittests/ADT/SmallVectorTest.cpp:118: Failure
Value of: v[i].getValue()
  Actual: 0
Expected: value
Which is: 2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 07:11:21 +00:00
Jean-Luc Duprat
617330909f Fix allocations of SmallVector and SmallPtrSet so they are more prone to
being power-of-two sized.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178332 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 05:45:22 +00:00
Michael Gottesman
ae07bf3ad3 Removed trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178329 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 05:13:07 +00:00
Akira Hatanaka
fda56e54cd [mips] Change type of accumulator registers to Untyped. Add two more accumulator
register classes for Mips64 and DSP-ASE.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178328 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 03:27:21 +00:00
Akira Hatanaka
c713e996d3 [mips] Define overloaded versions of storeRegToStack and loadRegFromStack.
No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 02:14:12 +00:00
Akira Hatanaka
8c0b9b03fe [mips] Add parameter Alignment to MipsFrameLowering's constructor.
No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178326 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 01:51:04 +00:00
Dan Gohman
1cbd401756 Revert r178166. According to Howard, this code is actually ok.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178319 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 00:13:08 +00:00
Jack Carter
af7da5cb99 [Mips Assembler] Add support for OR macro with imediate opperand
Mips assembler supports macros that allows the OR instruction 
to have an immediate parameter. This patch adds an instruction 
alias that converts this macro into a Mips ORI instruction. 

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:45:13 +00:00
Michael Liao
c26392aa5d Add support of RDSEED defined in AVX2 extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:41:26 +00:00
Michael Liao
258d9b7bc0 Enhance boolean simplification to handle 16-/64-bit RDRAND
- RDRAND always clears the destination value when a random value is not
  available (i.e. CF == 0). This value is truncated or zero-extended as
  the false boolean value to be returned. Boolean simplification needs
  to skip this 'zext' or 'trunc' node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:38:52 +00:00
Michael Liao
816f6d0ac7 Skip moving call address loading into callseq when targets prefer register indirect call.
To enable a load of a call address to be folded with that call, this
load is moved from outside of callseq into callseq. Such a moving
adds a non-glued node (that load) into a glued sequence. This non-glue
load is only removed when DAG selection folds them into a memory form
call instruction. When such instruction selection is disabled, it breaks
DAG schedule.

To prevent that, such moving is disabled when target favors register
indirect call.

Previous workaround disabling CALL32m/CALL64m insn selection is removed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178308 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:13:21 +00:00
Michael Gottesman
d02e46be1a Removed dead code from ObjCARCOpts relating to tracking objc_retainBlocks through the ARC Dataflow analysis. By the time we get to the ARC dataflow analysis, any objc_retainBlock calls are not optimizable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178306 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:08:44 +00:00
Chad Rosier
7ae3bb83c2 [fast-isel] Add a preemptive fix for the case where we fail to materialize an
immediate in a register.  I don't believe this should ever fail, but I see no
harm in trying to make this code bullet proof.

I've added an assert to ensure my assumtion is correct.  If the assertion fires
something is wrong and we should fix it, rather then just silently fall back to
SelectionDAG isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178305 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:04:47 +00:00
Jack Carter
94fcfaf3a9 [Mips Assembler] Add alias definitions for jal
Mips assembler allows following to be used as aliased instructions:
jal $rs for jalr $rs
jal $rd,$rd for jalr $rd,$rs

This patch provides alias definitions in td files and test cases to show the usage.

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:02:21 +00:00
Nadav Rotem
bad24f757d Add the X86 FMAs to the scheduling model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178303 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 22:54:45 +00:00
Bill Wendling
f2a2806baf Minor simplification.
Go ahead and use the full path for both the .gcno and .gcda files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178302 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 22:40:08 +00:00
Nadav Rotem
59af9d0bf4 Add the Haswell machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178301 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 22:34:46 +00:00
Nadav Rotem
0b6a69d4a1 Remove the unused port from the SandyBridge machine model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178300 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 22:32:41 +00:00
Michael Liao
5a8386e1df Add ADX CPUID detection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178299 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 22:29:53 +00:00
Eric Christopher
8e4cd40b27 These two are default in the constructor for MCAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 21:37:18 +00:00
Timur Iskhodzhanov
a46f82dbf9 Make Win32 put the SRet address into EAX, fixes PR15556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178291 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 21:30:04 +00:00
Hal Finkel
af0d148b20 Specify CPUs on the PPC bswap-load-store test
Otherwise, the CHECK-NOT's might trigger depending on the host's CPU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178287 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 20:35:18 +00:00
Hal Finkel
2544f221c5 Only enable 64-bit bswap DAG combines for PPC64
Compiling in 32-bit mode on a P7 would assert after 64-bit DAG combines were
added for bswap with load/store. This is because these combines are really only
valid in 64-bit mode, regardless of the CPU (and this was not being checked).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 20:23:46 +00:00
Michael Gottesman
3832eff354 Non optimizable objc_retainBlock calls are not forwarding.
Since we handle optimizable objc_retainBlocks through strength reduction
in OptimizableIndividualCalls, we know that all code after that point
will only see non-optimizable objc_retainBlock calls. IsForwarding is
only called by functions after that point, so it is ok to just classify
objc_retainBlock as non-forwarding.

<rdar://problem/13249661>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178285 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 20:11:30 +00:00
Michael Gottesman
0d92a3c600 [ObjCARC] Strength reduce objc_retainBlock -> objc_retain if the objc_retainBlock is optimizable.
If an objc_retainBlock has the copy_on_escape metadata attached to it
AND if the block pointer argument only escapes down the stack, we are
allowed to strength reduce the objc_retainBlock to to an objc_retain and
thus optimize it.

Current there is logic in the ARC data flow analysis to handle
this case which is complicated and involved making distinctions in
between objc_retainBlock and objc_retain in certain places and
considering them the same in others.

This patch simplifies said code by:

1. Performing the strength reduction in the initial ARC peephole
analysis (ObjCARCOpts::OptimizeIndividualCalls).

2. Changes the ARC dataflow analysis (which runs after the peephole
analysis) to consider all objc_retainBlock calls to not be optimizable
(since if the call was optimizable, we would have strength reduced it
already).

This patch leaves in the infrastructure in the ARC dataflow analysis to
handle this case, which due to 2 will just be dead code. I am doing this
on purpose to separate the removal of the old code from the testing of
the new code.

<rdar://problem/13249661>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 20:11:19 +00:00
Jyotsna Verma
810848d5b3 Hexagon: Replace switch-case in isDotNewInst with TSFlags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178281 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 19:44:04 +00:00
Hal Finkel
b52980be07 Fix bad indentation in r178276
Thanks to Bill Schmidt for pointing this out!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178280 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 19:43:12 +00:00
Jyotsna Verma
e41c7d4890 Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178279 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 19:34:49 +00:00
Akira Hatanaka
fc822ce34d Remove -O3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178278 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 19:34:14 +00:00
Bill Schmidt
53774a821d Use direct types in most PowerPC Altivec instructions and patterns.
This follows up Ulrich Weigand's work in PPCInstrInfo.td and
PPCInstr64Bit.td by doing the corresponding work for most of the
Altivec patterns.  I have not been able to do anything for the
following classes of instructions:

(1) Vector logicals.  These don't have corresponding intrinsics and
don't have a single obvious vector type.  So far as I can tell I need
to leave these as VRRC.  Affected instructions are:  VAND, VANDC,
VNOR, VOR, VXOR, V_SET0.

(2) Instructions that make use of vector shuffle.  The selection code
promotes all shuffles to v16i8, so any pattern that matches on a
shuffle is constrained.  I haven't found any way to make the patterns
match on their natural types, so I plan to leave these as VRRC.
Affected instructions are:  VMRG*, VSPLTB, VSPLTH, VSPLTW, VPKUHUM,
VPKUWUM.

No change in behavior is anticipated.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178277 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 19:27:24 +00:00
Hal Finkel
efdd4673d6 Add the PPC64 ldbrx/stdbrx instructions
These are 64-bit load/store with byte-swap, and available on the P7 and the A2.
Like the similar instructions for 16- and 32-bit words, these are matched in the
target DAG-combine phase against load/store-bswap pairs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178276 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 19:25:55 +00:00
Gordon Keiser
ce88835110 Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set.
They should always be zero-extended, not sign extended.  Added test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178275 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 19:22:28 +00:00
Gordon Keiser
93b10789c6 Testing commit access to llvm. Remove two lines of whitespace from the Thumb README.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178256 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 18:26:15 +00:00
Thomas Schwinge
7f5f06b818 Correct spelling of Git.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178254 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 18:06:20 +00:00
Rafael Espindola
30509ee8a3 Move test since it depends on the X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178249 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 17:01:28 +00:00
Jyotsna Verma
4f2ef94d6a Hexagon: Use multiclass for gp-relative instructions.
Remove noV4T gp-relative instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178246 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 16:25:57 +00:00
Howard Hinnant
aab2305454 Seciton 24.2.2 of the C++ standard, [iterator.iterators], Table 106
requires that the return type of *r for all iterators r be reference,
where reference is defined in [iterator.requirements.general]/p11 as
iterator_traits<X>::reference, and X is the type of r.

But in CFG.h, the dereference operator of PredIterator and SuccIterator
return pointer, not reference.

Furthermore the nested type reference is value_type&, which is not the
type returned from operator*().

This patch simply makes the iterator::reference type value_type*, which
is what the operator*() returns, and then re-lables the return type as
reference.

From a functionality point of view, the only difference is that the
nested reference type is now value_type* instead of value_type&.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178240 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 15:47:50 +00:00
Tim Northover
42a1b2f0b1 AArch64: implement GICv3 system registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178236 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 14:30:46 +00:00
Hal Finkel
c53ab4d77f Add the PPC64 popcntd instruction
PPC ISA 2.06 (P7, A2, etc.) has a popcntd instruction. Add this instruction and
tell TTI about it so that popcount-loop recognition will know about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 13:29:47 +00:00
Kostya Serebryany
f464481db0 [tsan] make sure memset/memcpy/memmove are not inlined in tsan mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 11:21:13 +00:00
Michael Gottesman
21fb0193b2 Revert "Updated ELF relocation test for .eh_frame section"
This reverts commit c8d6536422.

This broke a bunch of the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 05:14:26 +00:00
Jyotsna Verma
9f41d22467 Disable JIT/MCJIT tests in unittests/ExecutionEngine for the targets that don't support JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 03:38:29 +00:00