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3 Commits

Author SHA1 Message Date
Tim Northover
b1c1b8a78d ARM64: print fp immediates without using scientific notation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207669 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-30 16:13:34 +00:00
Louis Gerbarg
fc8fa8238d Make test/CodeGen/ARM64/vector-insertion.ll explicitly select neon syntax 
Change the command line vector-insertion.ll to explicitly set the neon syntax
to apple so that buildbots that default to other syntaxes won't fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206502 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-17 21:32:41 +00:00
Louis Gerbarg
5540570374 Improve ARM64 vector creation 
This patch improves the performance of vector creation in caseiswhere where
several of the lanes in the vector are a constant floating point value. It
also includes new patterns to fold together some of the instructions when the
value is 0.0f. Test cases included.

rdar://16349427

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206496 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-17 20:51:50 +00:00