Bob Wilson
ade57fa619
Add missing ARM and Thumb data layout info for vector types.
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Radar 8128745.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 04:41:08 +00:00
Bob Wilson
86fe66db3a
Reduce indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 04:12:31 +00:00
Evan Cheng
8acf67672b
Oops. IT block formation pass needs to be run at any optimization level.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106775 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 19:10:14 +00:00
Eli Friedman
761fa7af9e
Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106770 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 18:20:04 +00:00
Bob Wilson
789fef987f
PR7458: Try commuting Thumb2 instruction operands to put them into 2-address
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form so they can be narrowed to 16-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 16:50:20 +00:00
Bill Wendling
4b722108e2
We are missing opportunites to use ldm. Take code like this:
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void t(int *cp0, int *cp1, int *dp, int fmd) {
int c0, c1, d0, d1, d2, d3;
c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
/* ... */
}
It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 23:00:16 +00:00
Dale Johannesen
e39fdbe118
Do not do tail calls to external symbols. If the
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branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this. 8120438.
If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106662 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 18:52:34 +00:00
Jim Grosbach
5def57aaf4
When using libcall expansions for the atomic intrinsics, the explicit
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MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106631 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 16:08:49 +00:00
Bob Wilson
a3a204664d
Thumb1 functions using @llvm.returnaddress were not saving the incoming LR.
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Radar 8031193.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 22:04:24 +00:00
Dan Gohman
fe60104ac9
Use pre-increment instead of post-increment when the result is not used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106542 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 15:08:57 +00:00
Evan Cheng
4d54e5b2dd
Tail merging pass shall not break up IT blocks. rdar://8115404
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 01:18:16 +00:00
Bob Wilson
56a1a69a35
sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.
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Radar 8104310.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106484 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:27:34 +00:00
Jim Grosbach
a967d1121a
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
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being moved around away from the jump table it references. rdar://8104340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:27:27 +00:00
Evan Cheng
d95ea2da28
Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:21:14 +00:00
Dale Johannesen
b0ccb757b3
Fix PR 7433. Silly typo in non-Darwin ARM tail call
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handling, plus correct R9 handling in that mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:21:49 +00:00
Jim Grosbach
9cfcfeb24b
early exit for dbg_value instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106430 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 17:49:23 +00:00
Evan Cheng
859df5e9f9
Fix a crash caused by dereference of MBB.end(). rdar://8110842
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-20 00:54:38 +00:00
Bob Wilson
31ef8e6663
Remove a fixme comment that is no longer relevant.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106382 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 05:32:41 +00:00
Bob Wilson
dc076da4d2
Fix error message to match function name.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106381 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 05:32:09 +00:00
Evan Cheng
02ba9e19c7
Ignore dbg_value's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 02:36:21 +00:00
Evan Cheng
0110ac66eb
Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:01:32 +00:00
Evan Cheng
6523d2ff7f
Indentation and remove dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106362 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:11:54 +00:00
Dan Gohman
9559e3b99a
Silence compiler warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:02:06 +00:00
Evan Cheng
96c3da6436
Move ARM if-conversion before post-ra scheduling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:32:07 +00:00
Evan Cheng
3ee608c5aa
Update cmake list.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:12:10 +00:00
Evan Cheng
886459456c
Thumb2 hazard recognizer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:11:35 +00:00
Evan Cheng
86050dc8cc
Allow ARM if-converter to be run after post allocation scheduling.
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- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:09:54 +00:00
Jim Grosbach
ef6eb9c7ab
back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106342 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:03:10 +00:00
Jim Grosbach
68741be5e6
Enable Expand handling of atomics for subtargets that can't do them inline.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106336 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 22:35:32 +00:00
Bob Wilson
ebe99b2c19
Rewrite chained if's as switches and replace assertions with llvm_unreachable
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(as suggested in radar 8104405).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106318 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 21:32:42 +00:00
Dale Johannesen
51bd47edbc
Fix ARM/Thumb reversal in previous attempt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106314 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 21:07:47 +00:00
Jakob Stoklund Olesen
52c61ec164
When using ADDri to get the address of a stack object, 255 is a conservative
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limit on the offset that can be materialized without using the register
scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106312 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 20:59:25 +00:00
Dale Johannesen
10416803c1
An attempt to fix the problem Anton reported with
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ARM tail calls. Don't know if it works, but it
doesn't break Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106309 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 20:44:28 +00:00
Dale Johannesen
c66cdf74a9
Enable tail calls on ARM by default, with some
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basic tests.
This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
B.W <label in other function>
which it has not seen before, at least from llvm-based
compilers. I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 19:00:18 +00:00
Dan Gohman
a606d955de
Start TargetRegisterClass indices at 0 instead of 1, so that
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MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 18:13:55 +00:00
Dale Johannesen
df50d7e238
Last round of changes for ARM tail calls.
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Not turning them on yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106295 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 18:13:11 +00:00
Jakob Stoklund Olesen
0d8ba3303b
Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
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does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 16:49:33 +00:00
Dan Gohman
e368b460a2
Eliminate unnecessary uses of getZExtValue().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 14:22:04 +00:00
Stuart Hastings
3bf9125933
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
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addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 22:43:56 +00:00
Jim Grosbach
7072cf62a5
Thumb1 and any pre-v6 ARM target should use the libcall expansion of
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ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 02:02:03 +00:00
Jim Grosbach
c73993b678
simplify code a bit and add a more explanatory assert for cases that
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previously would result in 'cannot yet select' errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 01:37:00 +00:00
Jim Grosbach
7616b646f1
format and 80-column cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106173 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 23:45:49 +00:00
Jakob Stoklund Olesen
a2846b4bee
Don't attempt preserving conservative kill flags. We were doing it wrong.
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This is before LiveVariables anyway, where these kill flags are recalculated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106157 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 22:11:08 +00:00
Bob Wilson
07f6e805b1
Remove the hidden "neon-reg-sequence" option. The reg sequences are working
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now, so there's no need to disable them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 21:34:01 +00:00
Evan Cheng
46df4eb46e
Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 07:35:02 +00:00
Dale Johannesen
38d5f0441c
Add file missing from previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106058 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 22:24:08 +00:00
Dale Johannesen
6470a116f1
Next round of tail call changes. Register used in a tail
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call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 22:08:33 +00:00
Bob Wilson
827b2106fe
Add basic support for NEON modified immediates besides VMOV.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 19:05:35 +00:00
Daniel Dunbar
f4a7bf4ec3
Add <cstddef> include to get ptrdiff_t, for gcc-4.6; patch by Dimitry Andric.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 14:50:42 +00:00
Bob Wilson
14f1d4e74b
VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 05:51:27 +00:00