Commit Graph

13 Commits

Author SHA1 Message Date
Daniel Dunbar
c22e0b2443 Update llvm-mc / MCAsmStreamer to print the instruction using the actual target
specific printer (this only works on x86, for now).
 - This makes it possible to do some correctness checking of the parsing and
   matching, since we can compare the results of 'as' on the original input, to
   those of 'as' on the output from llvm-mc.

 - In theory, we could now have an easy ATT -> Intel syntax converter. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
Daniel Dunbar
1095f2ae26 llvm-mc/AsmParser: Match hard coded registers (e.g. 'shldl %cl, %eax, %eax')
We now match all of 403.gcc (as emitted by clang). :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78750 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 23:23:44 +00:00
Daniel Dunbar
0db68f4e3a llvm-mc/X86: Parse '*' correctly (in the way the matcher expects).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78642 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 05:00:25 +00:00
Daniel Dunbar
ea6408f8cd llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands.
- This drops us to 123 ambiguous instructions (previously ~500) on X86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78636 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 02:59:53 +00:00
Daniel Dunbar
44f63f9335 llvm-mc/AsmParser: Disambiguate i64i8imm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78598 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 21:06:41 +00:00
Daniel Dunbar
5fe6338ac8 llvm-mc/AsmParser: Implement user defined super classes.
- We can now discriminate SUB32ri8 from SUB32ri, for example.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78530 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 07:20:21 +00:00
Daniel Dunbar
a3741fa28b llvm-mc/AsmMatcher: Improve match code.
- This doesn't actually improve the algorithm (its still linear), but the
   generated (match) code is now fairly compact and table driven. Still need a
   generic string matcher.

 - The table still needs to be compressed, this is quite simple to do and should
   shrink it to under 16k.

 - This also simplifies and restructures the code to make the match classes more
   explicit, in anticipation of resolving ambiguities.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78461 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 07:50:56 +00:00
Daniel Dunbar
7ddca30f31 Disable X86 AsmMatcher for now, it is causing gcc-4.0 to run out of memory on
i386-apple-darwin9. This presumably will get fixed once the generated code
improves.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78379 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 08:45:03 +00:00
Daniel Dunbar
20927f26fc llvm-mc/AsmMatcher: Move to a slightly more sane matching design.
- Still not very sane, but a least its not 60k lines on X86. :)

 - In terms of correctness, currently some things are hard wired for X86, and we
   still don't properly resolve ambiguities (this is ignoring the instructions
   we don't even match due to funny .td stuff or other corner cases).

The high level changes:
 1. Represent tokens which are significant for matching explicitly as separate
    operands. This uniformly handles not only the instruction mnemonic, but
    also 'signficiant' syntax like the '*' in "call * ...".

 2. Separate the matching of operands to an instruction from the construction of
    the MCInst. In theory this can be done during matching, but since the number
    of variations is small I think it makes sense to decompose the problems.

 3. Improved a few of the mechanisms to at least successfully flatten / tokenize
    the assembly strings for PowerPC and ARM.

 4. The comment at the top of AsmMatcherEmitter.cpp explains the approach I'm
    moving towards for handling ambiguous instructions. The high-bit is to infer
    a partial ordering of the operand classes (and force the user to specify one
    if we can't) and use that to resolve ambiguities.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78378 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 08:26:05 +00:00
Daniel Dunbar
022e2a84a8 llvm-mc/X86: Sketch match functions for immediates and memory operands.
Also, change scale value to always be 1 when unspecified to machine MachineInst
encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77728 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 20:53:16 +00:00
Daniel Dunbar
b6804e9126 Add this test back, the check pattern was too strict.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77662 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 03:11:49 +00:00
Daniel Dunbar
527695dd66 Remove this test while I figure out why it is failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77659 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 02:46:36 +00:00
Daniel Dunbar
a027d222e1 llvm-mc: Match a few X86 instructions.
- This is "experimental" code, I am feeling my way around and working out the
   best way to do things (and learning tblgen in the process). Comments welcome,
   but keep in mind this stuff will change radically.

 - This is enough to match "subb" and friends, but not much else. The next step is to
   automatically generate the matchers for individual operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77657 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 02:32:59 +00:00