Commit Graph

29 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
98d9648de7 Change the RAGreedy register assignment order so large live ranges are allocated first.
This is based on the observation that long live ranges are more difficult to
allocate, so there is a better chance of solving the puzzle by handling the big
pieces first. The allocator will evict and split long alive ranges when they get
in the way.

RABasic is still using spill weights for its priority queue, so the interface to
the queue has been virtualized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126259 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22 23:01:52 +00:00
Jakob Stoklund Olesen
ba05c01dab Add VirtRegMap::rewrite() and use it in the new register allocators.
The rewriter works almost identically to -rewriter=trivial, except it also
eliminates any identity copies.

This makes the new register allocators independent of VirtRegRewriter.cpp which
will be going away at the same time as RegAllocLinearScan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125967 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18 22:03:18 +00:00
Jakob Stoklund Olesen
febb0bd0b9 Trim debugging output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125802 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18 00:32:47 +00:00
Jakob Stoklund Olesen
0db841f9c2 Add basic register allocator statistics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125789 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-17 22:53:48 +00:00
Jakob Stoklund Olesen
2710638db2 Evict a lighter single interference before attempting to split a live range.
Registers are not allocated strictly in spill weight order when live range
splitting and spilling has created new shorter intervals with higher spill
weights.

When one of the new heavy intervals conflicts with a single lighter interval,
simply evict the old interval instead of trying to split the heavy one.

The lighter interval is a better candidate for splitting, it has a smaller use
density.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125151 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-09 01:14:03 +00:00
Jakob Stoklund Olesen
89cab93fe9 Pass a Banner argument to the machine code verifier both from
createMachineVerifierPass and MachineFunction::verify.

The banner is printed before the machine code dump, just like the printer pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122113 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 00:06:56 +00:00
Jakob Stoklund Olesen
af24964251 Make the -verify-regalloc command line option available to base classes as
RegAllocBase::VerifyEnabled.

Run the machine code verifier in a few interesting places during RegAllocGreedy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122107 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 23:16:35 +00:00
Jakob Stoklund Olesen
16999da951 Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:10:48 +00:00
Jakob Stoklund Olesen
4a84cce3ed Use TRI::printReg instead of AbstractRegisterDescription when printing
LiveIntervalUnions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 18:53:47 +00:00
Jakob Stoklund Olesen
533f58ecdd Add named timer groups for the different stages of register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121604 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-11 00:19:56 +00:00
Jakob Stoklund Olesen
4680dec5fb Move MRI into RegAllocBase. Clean up debug output a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121599 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 23:49:00 +00:00
Andrew Trick
b853e6c370 Added register reassignment prototype to RAGreedy. It's a simple
heuristic to reshuffle register assignments when we can't find an
available reg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121388 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 18:15:21 +00:00
Jakob Stoklund Olesen
d0bec3e62c Store (priority,regnum) pairs in the priority queue instead of providing an
abstract priority queue interface in subclasses that want to override the
priority calculations.

Subclasses must provide a getPriority() implementation instead.

This approach requires less code as long as priorities are expressable as simple
floats, and it avoids the dangers of defining potentially expensive priority
comparison functions.

It also should speed up priority_queue operations since they no longer have to
chase pointers when comparing registers. This is not measurable, though.

Preferably, we shouldn't use floats to guide code generation. The use of floats
here is derived from the use of floats for spill weights. Spill weights have a
dynamic range that doesn't lend itself easily to a fixpoint implementation.

When someone invents a stable spill weight representation, it can be reused for
allocation priorities.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121294 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 22:22:41 +00:00
Jakob Stoklund Olesen
1b19dc1d8b Move RABasic::addMBBLiveIns to the base class, it is generally useful.
Minor optimization to the use of IntervalMap iterators. They are fairly
heavyweight, so prefer SI.valid() over SI != end().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121217 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 01:06:06 +00:00
Jakob Stoklund Olesen
953af2c3c5 Switch LiveIntervalUnion from std::set to IntervalMap.
This speeds up RegAllocBasic by 20%, not counting releaseMemory which becomes
way faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 23:18:47 +00:00
Jakob Stoklund Olesen
2b38c51f0e Simplify assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121162 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 18:51:27 +00:00
Andrew Trick
18c57a8a09 Coding style. No significant functionality. Abandon linear scan style
in favor of the widespread llvm style. Capitalize variables and add
newlines for visual parsing. Rename variables for readability.
And other cleanup.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120490 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:18:47 +00:00
Benjamin Kramer
c62feda741 Namespacify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120146 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-25 16:42:51 +00:00
Andrew Trick
316df4bfe3 RABasic fix. Regalloc is responsible for updating block live ins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 02:57:05 +00:00
Andrew Trick
13bdbb0544 Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119895 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 02:43:55 +00:00
Andrew Trick
8a83d54528 Check TRI->getReservedRegs because other allocators do it. Even though
it makes no sense for allocation_order iterators to visit reserved regs.
The inline spiller depends on AliasAnalysis.
Manage the Query state to avoid uninitialized or stale results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118800 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 17:46:29 +00:00
Andrew Trick
f4baeaf848 RABasic is nearly functionally complete. There are a few remaining
benchmarks hitting an assertion.
Adds LiveIntervalUnion::collectInterferingVRegs.
Fixes "late spilling" by checking for any unspillable live vregs among
all physReg aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 19:18:47 +00:00
Andrew Trick
071d1c063f Adds RABasic verification and tracing.
(retry now that the windows build is green)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118630 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 21:04:34 +00:00
Andrew Trick
32d9aeb1df Reverting r118604. Windows build broke.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118613 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 19:47:51 +00:00
Andrew Trick
39a5ce46a5 Adds RABasic verification and tracing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118604 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 19:01:17 +00:00
Andrew Trick
e141a4960f Adds support for spilling previously allocated live intervals to
handle cases in which a register is unavailable for spill code.
Adds LiveIntervalUnion::extract. While processing interferences on a
live virtual register, reuses the same Query object for each
physcial reg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118423 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 18:02:08 +00:00
Jakob Stoklund Olesen
964bc25e5a Let RegAllocBasic require MachineDominators - they are already available and
splitting needs them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 20:39:26 +00:00
Andrew Trick
e16eecc323 Jakob's review of the basic register allocator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 18:34:01 +00:00
Andrew Trick
14e8d71cc9 This is a prototype of an experimental register allocation
framework. It's purpose is not to improve register allocation per se,
but to make it easier to develop powerful live range splitting. I call
it the basic allocator because it is as simple as a global allocator
can be but provides the building blocks for sophisticated register
allocation with live range splitting. 

A minimal implementation is provided that trivially spills whenever it
runs out of registers. I'm checking in now to get high-level design
and style feedback. I've only done minimal testing. The next step is
implementing a "greedy" allocation algorithm that does some register
reassignment and makes better splitting decisions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117174 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 23:09:15 +00:00