5 Commits

Author	SHA1	Message	Date
Andrew Trick	922d314e8f	Instruction scheduling itinerary for Intel Atom. ... Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8	2012-02-01 23:20:51 +00:00
Chris Lattner	d2bf432b2b	Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145171 91177308-0d34-0410-b5e6-96231b3b80d8	2011-11-27 06:54:59 +00:00
Evan Cheng	f06e6c2ba7	Catch more cases where 2-address pass should 3-addressify instructions. rdar://9002648. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126811 91177308-0d34-0410-b5e6-96231b3b80d8	2011-03-02 01:08:17 +00:00
Evan Cheng	4d96c638af	After 3-addressifying a two-address instruction, update the register maps; add a missing check when considering whether it's profitable to commute. rdar://8977508. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125259 91177308-0d34-0410-b5e6-96231b3b80d8	2011-02-10 02:20:55 +00:00
Dan Gohman	b75e8642a6	Add some tests and update an existing test to reflect recent ... x86 isel peeps. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92509 91177308-0d34-0410-b5e6-96231b3b80d8	2010-01-04 20:53:54 +00:00