131 Commits

Author SHA1 Message Date
Tom Stellard
573630a020 R600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
This s_mov_b32 will write to a virtual register from the M0Reg
class and all the ds instructions now take an extra M0Reg explicit
argument.

This change is necessary to prevent issues with the scheduler
mixing together instructions that expect different values in the m0
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222583 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-21 22:31:44 +00:00
Matt Arsenault
b556213712 R600/SI: Set hasSideEffects = 0 on load and store instructions.
Assuming unmodeled side effects interferes with some scheduling
opportunities.

Don't put it in the base class of DS instructions since there
are a few weird effecting, non load/store instructions there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222285 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 23:57:33 +00:00
Matt Arsenault
8fd3b90c3f R600/SI: Use S_BFE_I64 for 64-bit sext_inreg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222012 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-14 18:18:16 +00:00
Matt Arsenault
01ab7a869d R600/SI: Use s_movk_i32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221922 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-13 20:44:23 +00:00
Matt Arsenault
0fed4c6a45 R600/SI: Fix definition for s_cselect_b32
These were directly using the old base instruction
class, and specifying the wrong register classes
for operands. The operands can be the other special
inputs besides SGPRs. The op name was also being
directly used for the asm string, so this was printed
without any operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221921 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-13 20:23:36 +00:00
Matt Arsenault
b44e43623d R600/SI: Get rid of FCLAMP_SI pseudo
It's not necessary. Also use complex patterns to allow
src modifier usage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221916 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-13 19:49:04 +00:00
Matt Arsenault
ecb144e2d1 R600/SI: Fix omod display for VOP3b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221387 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 19:35:00 +00:00
Tom Stellard
8eaed0f63d R600/SI: Change all instruction assembly names to lowercase.
This matches the format produced by the AMD proprietary driver.

//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
   you want to convert to this script as arguments).
//==================================================================//

; This was necessary on my system so that A-Z in sed would match only
; upper case.  I'm not sure why.
export LC_ALL='C'

TEST_FILES="$*"

MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`

for f in $TEST_FILES; do
  # Check that there are SI tests:
  grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
  if [ $? -eq 0 ]; then
    for match in $MATCHES; do
      sed -i -e "s/\([ :]$match\)/\L\1/" $f
    done

    # Try to get check lines with partial instruction names
    sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
  fi
done

sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll

//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//

export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 14:50:53 +00:00
Matt Arsenault
e2463284fc R600/SI: Rename div_scale dest operands to match documentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221291 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 20:29:20 +00:00
Matt Arsenault
fc9fda5443 R600/SI: Change how DS offsets are printed
Match SC by using offset/offset0/offset1 and printing
in decimal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219537 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-10 22:16:07 +00:00
Tom Stellard
806e08c5a0 R600/SI: Refactor VOP3 instruction defs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219256 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-07 23:51:41 +00:00
Tom Stellard
96c9ebbd04 R600/SI: Refactor VOPC instruction defs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219255 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-07 23:51:39 +00:00
Tom Stellard
40949737c4 R600/SI: Refactor VOP2 instruction defs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-07 23:51:38 +00:00
Tom Stellard
6bf4c41242 R600/SI: Refactor VOP1 instruction defs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219253 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-07 23:51:34 +00:00
Tom Stellard
f7082f9bd7 R600/SI: Add a generic pseudo EXP instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218767 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-01 14:44:45 +00:00
Tom Stellard
cbb63311cd R600/SI: Add generic pseudo MTBUF instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218766 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-01 14:44:43 +00:00
Tom Stellard
f69ae4815a R600/SI: Add generic pseudo SMRD instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218765 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-01 14:44:42 +00:00
Matt Arsenault
28233d3a63 R600/SI: Fix printing of clamp and omod
No tests for omod since nothing uses it yet, but
this should get rid of the remaining annoying trailing
zeros after some instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218692 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-30 19:49:48 +00:00
Matt Arsenault
532a5c7dc6 R600/SI: Update VOP3b to not include obsolete operands
abs / neg are now part of the srcN_modifiers operands

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218691 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-30 19:49:43 +00:00
Tom Stellard
29d48e6a49 R600/SI: Add support for global atomic add
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218457 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 18:30:26 +00:00
Tom Stellard
33aca6d4a0 R600/SI: Clean up checks for legality of immediate operands
There are new register classes VCSrc_* which represent operands that
can take an SGPR, VGPR or inline constant.  The VSrc_* class is now used
to represent operands that can take an SGPR, VGPR, or a 32-bit
immediate.

This allows us to have more accurate checks for legality of
immediates, since before we had no way to distinguish between operands
that supported any 32-bit immediate and operands which could only
support inline constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218334 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-23 21:26:25 +00:00
Tom Stellard
e1bc40b1e6 Revert "R600/SI: Add support for global atomic add"
This reverts commit r218254.

The global_atomics.ll test fails with asserts disabled.  For some reason,
the compiler fails to produce the atomic no return variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218257 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-22 16:44:04 +00:00
Tom Stellard
6d625ad495 R600/SI: Add support for global atomic add
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-22 15:35:35 +00:00
Matt Arsenault
d189a0407d R600/SI: Add preliminary support for flat address space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217777 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 15:41:53 +00:00
Matt Arsenault
ef4bb30475 R600/SI: Replace LDS atomics with no return versions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217379 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-08 15:07:31 +00:00
Matt Arsenault
f1cd7ce098 R600/SI: Add InstrMapping for noret atomics.
Only handles LDS atomics for now, and will be used
to replace atomics with no uses with the no return
versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217378 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-08 15:07:27 +00:00
Matt Arsenault
f4d57e7874 R600/SI: Use mad for fsub + fmul
We can use a negate source modifier to match
this for fsub.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216735 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-29 16:01:14 +00:00
Tom Stellard
f50f927d65 R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216279 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-22 18:49:35 +00:00
Tom Stellard
ec4cb3346d R600/SI: Use a ComplexPattern for DS loads and stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216278 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-22 18:49:33 +00:00
Tom Stellard
9048dc6867 R600/SI: Use correct helper class for DS_WRITE2 instructions
DS_1A uses a single offset encoding, so offset1 wasn't being
encoded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216276 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-22 18:49:28 +00:00
Tom Stellard
13f4476c55 R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variant
This saves us from having to copy a 64-bit 0 value into VGPRs for
BUFFER_* instruction which only have a 12-bit immediate offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215399 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-11 22:18:17 +00:00
Tom Stellard
f56c55d003 R600/SI: Add an _OFFEN variant MUBUF_STORE_* and use it for scratch writes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215398 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-11 22:18:14 +00:00
Tom Stellard
728d0e4218 R600/SI: Clear lds bit on MUBUF instructions used for private stores
This bit was left uninitialized, which was causing some random failures
of piglit tests.

NOTE: This is a candidate for the 3.5 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215396 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-11 22:18:09 +00:00
Tom Stellard
94dfb8818d R600/SI: Update MUBUF assembly string to match AMD proprietary compiler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214866 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-05 14:48:12 +00:00
Eric Christopher
9f85dccfc6 Remove the TargetMachine forwards for TargetSubtargetInfo based
information and update all callers. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 21:25:23 +00:00
Matt Arsenault
fa76ba82f2 R600/SI: Fix definitions for ds_read2 / ds_write2 instructions.
These were just wrong, using the wrong register classes
and store2 was missing an operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214756 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 18:49:22 +00:00
Matt Arsenault
fc65cf649c R600/SI: Fix extra whitespace in asm str
This slipped in in r214467, so something like

V_MOV_B32_e32  v0, ... is now printed with 2 spaces
between the instruction name and first operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214660 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-03 05:27:14 +00:00
Matt Arsenault
76db85a36f R600/SI: Don't display GDS bit for read2
This isn't displayed for any other instructions anymore,
and isn't ever used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214523 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 17:00:26 +00:00
Tom Stellard
17c8fefc9f R600/SI: Do abs/neg folding with ComplexPatterns
Abs/neg folding has moved out of foldOperands and into the instruction
selection phase using complex patterns.  As a consequence of this
change, we now prefer to select the 64-bit encoding for most
instructions and the modifier operands have been dropped from
integer VOP3 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214467 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:39 +00:00
Tom Stellard
163d8ce61f R600/SI: Refactor VOP3 instruction definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213571 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:44:29 +00:00
Tom Stellard
d7858afe79 R600/SI: Initailize encoding fields of unused VOP3 modifiers to 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213564 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:12:40 +00:00
Tom Stellard
0794af86a1 R600/SI: Initialize unused VOP3 sources to 0 instead of SIOperand.ZERO
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213563 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:12:37 +00:00
Tom Stellard
9787e8c76b R600/SI: Add instruction shrinking pass
This pass converts 64-bit instructions to 32-bit when possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213561 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 16:55:33 +00:00
Tom Stellard
df99a7f5dc R600/SI: VOPC instructions explicitly define VCC
Therefore we don't need to add it to the implict defs list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213558 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 16:27:24 +00:00
Tom Stellard
3280804237 R600/SI: Use scratch memory for large private arrays
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213551 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 15:45:01 +00:00
Tom Stellard
59b8363f8a R600/SI: Remove vaddr operand from BUFFER_LOAD_*_OFFSET instructions
This operand is never used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213549 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 15:44:55 +00:00
Tom Stellard
b664d47cb0 R600/SI: Store constant initializer data in constant memory
This implements a solution for constant initializers suggested
by Vadim Girlin, where we store the data after the shader code
and then use the S_GETPC instruction to compute its address.

This saves use the trouble of creating a new buffer for constant data
and then having to pass the pointer to the kernel via user SGPRs or the
input buffer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213530 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 14:01:14 +00:00
Tom Stellard
ad9769a118 R600/SI: Use a custom encoding method for simm16 in SOPP branch instructions
This allows us to explicitly define the type of fixup that is needed,
so we can distinguish this from future fixup types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213527 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 14:01:08 +00:00
Tom Stellard
4a70647269 R600/SI: Use a ComplexPattern for ADDR64 addressing of MUBUF loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212217 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-02 20:53:56 +00:00
Tom Stellard
11580ee62d R600/SI: Use a ComplexPattern for MUBUF stores
Now that non-leaf ComplexPatterns are allowed we can fold all the MUBUF
store patterns into the instruction definition.  We will also be able to
reuse this new ComplexPattern for MUBUF loads and atomic operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211644 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-24 23:33:07 +00:00