Craig Topper
cc30006391
Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 07:50:31 +00:00
Craig Topper
86c7c583a3
Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149216 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 01:10:15 +00:00
Anton Korobeynikov
6edd5884c9
Cleanups for EABI standard functions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149195 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-29 09:11:50 +00:00
Anton Korobeynikov
f349cb8f33
Use base AAPCS for varargs functions even for AAPCS-VFP CC
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149194 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-29 09:06:09 +00:00
Bob Wilson
7750ff1e3c
Add a note about a potential optimization for clz/ctz patterns for ARM
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(and other targets).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149182 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-28 18:30:07 +00:00
James Molloy
2d8955a77c
Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
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Fixes PR11877
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-28 15:58:32 +00:00
Devang Patel
a28101e61a
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27 19:48:28 +00:00
Craig Topper
3982b3cc7b
Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27 07:09:40 +00:00
Jim Grosbach
cb5dca3815
Keep source location information for X86 MCFixup's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149106 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27 00:51:27 +00:00
Jim Grosbach
6b4bcd69d0
Better user diagnostics for more ARM MachO relocation errors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149102 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27 00:37:12 +00:00
Jim Grosbach
ebd4c05c3c
Better diagnostic for malformed .org assembly directive.
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Provide source line number information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27 00:37:08 +00:00
Jim Grosbach
42e6bd38e0
Keep source information, if available, around for ARM Fixups.
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Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.
Before:
LLVM ERROR: unknown ARM fixup kind!
After:
x.s:6:5: error: unsupported relocation on symbol
beq bar
^
rdar://9800182
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149093 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 23:20:15 +00:00
Jakob Stoklund Olesen
53fa56e8dc
Handle call-clobbered ymm registers on Win64.
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The Win64 calling convention has xmm6-15 as callee-saved while still
clobbering all ymm registers.
Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the
ymm registers, and mark that as call-clobbered. This allows live xmm
registers across calls.
This hack wouldn't be necessary with RegisterMask operands representing
the call clobbers, but they are not quite operational yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149088 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 22:59:28 +00:00
Jim Grosbach
ef4d3ebe2a
Tidy up. Fix mismatched return types for error handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 15:56:45 +00:00
James Molloy
34982576a4
Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
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This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 09:25:43 +00:00
Victor Umansky
668f7ac9e4
Fix for the following bug in AVX codegen for double-to-int conversions:
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. "fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
. Currently for AVX mode for <4xdouble> and <8xdouble> the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
. Consequently, the conversion produces incorrect numbers.
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode.
As .fp_to_sint. DAG node operation is used only for lowering of "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149056 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 08:51:39 +00:00
Craig Topper
a3937416e4
Add HasXOP predicate check covering a bunch of XOP intrinsic patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149054 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 07:51:55 +00:00
Craig Topper
15388c4666
Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149053 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 07:31:30 +00:00
Craig Topper
e566cd0f4d
Remove some more patterns by custom lowering intrinsics to target specific nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149052 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 07:18:03 +00:00
Anton Korobeynikov
4a99f59aef
Properly emit ctors / dtors with priorities into desired sections
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and let linker handle the rest.
This finally fixes PR5329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148990 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 22:24:19 +00:00
Jim Grosbach
74423e32ce
ARM assemly parsing and validation of IT instruction.
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"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148969 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 19:52:01 +00:00
Chris Lattner
9748479590
fix a bug I introduced in r148929, this is not a splat!
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Thanks to Eli for noticing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148947 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 09:56:22 +00:00
Craig Topper
969ba287cd
Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148933 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 06:43:11 +00:00
Chris Lattner
4ca829e895
use ConstantVector::getSplat in a few places.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148929 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 06:02:56 +00:00
Craig Topper
4bb3f34b22
Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148927 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 05:37:32 +00:00
Craig Topper
bce73e0a8c
Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 04:42:03 +00:00
Akira Hatanaka
4bd73cac6a
Mark 64-bit register RA_64 unused too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148918 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 04:19:22 +00:00
Akira Hatanaka
de5a0b65c2
Modify MipsFrameLowering::emitPrologue and emitEpilogue.
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- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit.
- Change the types of variables so that they are sufficiently large to handle
64-bit pointers.
- Emit instructions to set register $28 in a function prologue after
instructions which store callee-saved registers have been emitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148917 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 04:12:04 +00:00
Akira Hatanaka
36e91e9599
Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate to
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expand offsets that do not fit in the 16-bit immediate field of load and store
instructions. Also change the types of variables so that they are sufficiently
large to handle 64-bit pointers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148916 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 03:55:10 +00:00
Craig Topper
042883f5da
Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148914 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 03:52:09 +00:00
NAKAMURA Takumi
50da3cb0f8
MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc.
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inttypes.h is not supplied in msvc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148912 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 03:34:41 +00:00
NAKAMURA Takumi
e0794d331a
Target/Mips: Unbreak CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148909 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 03:15:46 +00:00
Akira Hatanaka
57fa38225c
Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added.
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Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148908 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 03:01:35 +00:00
Akira Hatanaka
dc81eae9d2
Add class MipsAnalyzeImmediate which comes up with an instruction sequence to
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load an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148900 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 01:43:36 +00:00
Jim Grosbach
a57a36abe7
NEON VLD4(all lanes) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 00:01:08 +00:00
Jim Grosbach
6cd6a6824f
Tidy up. Rename VLD4DUP patterns for consistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148883 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 23:47:07 +00:00
Jim Grosbach
5e59f7e15e
NEON VLD3(all lanes) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 23:47:04 +00:00
Akira Hatanaka
25dae8f4a3
Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,
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which is what N32/64 does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148875 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 23:18:43 +00:00
Akira Hatanaka
08067b26f7
Pass CCState by reference.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148871 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 22:07:36 +00:00
Akira Hatanaka
e6e4b3a002
Pattern for f32 to i64 conversion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 22:05:25 +00:00
Devang Patel
3b96e1fe3b
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 21:43:36 +00:00
Akira Hatanaka
5387f2e4f3
64-bit sign extension in register instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148862 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 21:41:09 +00:00
Jim Grosbach
88a54de799
NEON VST4(one lane) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148836 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 18:53:13 +00:00
Owen Anderson
4f8dc7b17a
Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 18:37:29 +00:00
Jim Grosbach
e983a134e7
NEON VLD4(one lane) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148832 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 18:37:25 +00:00
Jim Grosbach
1ac2060678
NEON Two-operand assembly aliases for VSRA.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148821 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:55:36 +00:00
Jim Grosbach
5e497d3992
NEON Two-operand assembly aliases for VSLI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:49:15 +00:00
Jim Grosbach
d8ee0cc4e8
NEON Two-operand assembly aliases for VSRI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:46:58 +00:00
Jim Grosbach
78d13e191e
NEON add correct predicates for some asm aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148815 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:23:29 +00:00
Chris Lattner
29cc6cb4d1
C++, CBE, and TLOF support for ConstantDataSequential
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148805 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 14:17:05 +00:00