6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-10 06:54:54 +00:00
Code Issues Projects Releases Wiki Activity
93,419 Commits 39 Branches 0 Tags 277 MiB
cedcfee405
Commit Graph

5 Commits

Author SHA1 Message Date
Evan Cheng
2dad6b501b Try to make these tests more portable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164320 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-20 21:35:21 +00:00
Evan Cheng
d10eab0a95 Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte 
aligned address. Based on patch by David Peixotto.

Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment
hints. rdar://12090772, rdar://12238782


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164089 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 01:42:45 +00:00
Jim Grosbach
ffc658b056 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:03:21 +00:00
Cameron Zwarich
5af60ce2a8 Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129468 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:01:19 +00:00
Cameron Zwarich
c0e6d780cd Add a ARM-specific SD node for VBSL so that forms with a constant first operand 
can be recognized. This fixes <rdar://problem/9183078>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128584 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-30 23:01:21 +00:00