Commit Graph

11 Commits

Author SHA1 Message Date
David Blaikie
7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00
Vladimir Medic
d89ac8f158 Replace obsolete -mattr=n64 command line option with -target-abi=n64. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230628 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-26 12:29:48 +00:00
Daniel Sanders
0ee5398b7f [mips][mips64r6] Improve tests affected by the changes to multiplies and divides
Summary:
MIPS32r6/MIPS64r6 support has not been added yet.

inlineasm-cnstrnt-reg.ll:
  Explicitly specify the CPU since it will not work on MIPS32r6/MIPS64r6
  when -integrated-as is the default. We can't change the mnemonic since the
  LO register is an implicit def of mtlo and MIPS32r6/MIPS64r6 has no
  instructions that use LO.

2008-08-01-AsmInline.ll:
  Explicitly specify the CPU since MIPS32r6/MIPS64r6 will correctly emit
  different code and this is a regression test.

mips64instrs.ll and mips64muldiv.ll
  Check registers and the way the multiply is used in m1

divrem.ll
  Check registers and use multiple filecheck prefixes to limit redundancy

Reviewers: vmedic, jkolek, zoran.jovanovic, matheusalmeida

Reviewed By: matheusalmeida

Subscribers: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3894

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210656 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 15:48:00 +00:00
Akira Hatanaka
bfb07b1054 [mips] Properly parse registers that appear in inline-asm constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 00:21:25 +00:00
Akira Hatanaka
cb9dd72fdc Have getRegForInlineAsmConstraint return the correct register class when target
is Mips64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147516 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 02:45:01 +00:00
Akira Hatanaka
fa341d919f Fix test cases to use FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145716 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 22:28:09 +00:00
Duncan Sands
cdd4f8c7cb Correct bogus module triple specifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 10:48:29 +00:00
Dan Gohman
fce288fc91 Eliminate more uses of llvm-as and llvm-dis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 00:09:15 +00:00
Dan Gohman
fea1dd0804 Remove obsolete -f flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79992 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-25 15:38:29 +00:00
Duncan Sands
7cb07874dc Turn on LegalizeTypes, the new type legalization
codegen infrastructure, by default.  Please report
any breakage to the mailing lists.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58232 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-27 08:42:46 +00:00
Bruno Cardoso Lopes
0b4e136c74 Batch 5 of Mips CodeGen tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54510 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-08 04:09:57 +00:00