Commit Graph

28033 Commits

Author SHA1 Message Date
Rafael Espindola
7e9df19d5f Use printable names to implement directional labels.
This changes the implementation of local directional labels to use a dedicated
map. With that it can then just use CreateTempSymbol, which is what the rest
of MC uses.

CreateTempSymbol doesn't do a great job at making sure the names are unique
(or being efficient when the names are not needed), but that should probably
be fixed in a followup patch.

This fixes pr18928.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203826 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 18:09:26 +00:00
Tom Stellard
47feea0802 R600: LDS instructions shouldn't implicitly define OQAP
LDS instructions are pseudo instructions which model
the OQAP defs and uses within a single instruction.

This fixes a hang in the opencv MedianFilter tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203818 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 17:13:04 +00:00
Hans Wennborg
c8ed0db5aa [ARM] Use symbolic register names in .cfi directives only with IAS (PR19110)
This is a follow-up to r203635. Saleem pointed out that since symbolic register
names are much easier to read, it would be good if we could turn them off only
when we really need to because we're using an external assembler.

Differential Revision: http://llvm-reviews.chandlerc.com/D3056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203806 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 15:56:41 +00:00
Manuel Jacob
f8909fa140 CodeGenPrep: sink extends of illegal types into use block.
Summary:
This helps the instruction selector to lower an i64 * i64 -> i128
multiplication into a single instruction on targets which support it.

This is an update of D2973 which was reverted because of a bug reported
as PR19084.

Reviewers: t.p.northover, chapuni

Reviewed By: t.p.northover

CC: llvm-commits, alex, chapuni

Differential Revision: http://llvm-reviews.chandlerc.com/D3021

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203797 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 13:36:25 +00:00
Elena Demikhovsky
3d1ae71813 AVX-512: masked load/store + intrinsics for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203790 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 12:05:52 +00:00
Tim Northover
2d9f3bf9f9 AArch64: error when both positional & named operands are used.
Only one instruction pair needed changing: SMULH & UMULH. The previous
code worked, but MC was doing extra work treating Ra as a valid
operand (which then got completely overwritten in MCCodeEmitter).

No behaviour change, so no tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203772 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 09:00:13 +00:00
Hal Finkel
ab849adec4 [PowerPC] Initial support for the VSX instruction set
VSX is an ISA extension supported on the POWER7 and later cores that enhances
floating-point vector and scalar capabilities. Among other things, this adds
<2 x double> support and generally helps to reduce register pressure.

The interesting part of this ISA feature is the register configuration: there
are 64 new 128-bit vector registers, the 32 of which are super-registers of the
existing 32 scalar floating-point registers, and the second 32 of which overlap
with the 32 Altivec vector registers. This makes things like vector insertion
and extraction tricky: this can be free but only if we force a restriction to
the right register subclass when needed. A new "minipass" PPCVSXCopy takes care
of this (although it could do a more-optimal job of it; see the comment about
unnecessary copies below).

Please note that, currently, VSX is not enabled by default when targeting
anything because it is not yet ready for that.  The assembler and disassembler
are fully implemented and tested. However:

 - CodeGen support causes miscompiles; test-suite runtime failures:
      MultiSource/Benchmarks/FreeBench/distray/distray
      MultiSource/Benchmarks/McCat/08-main/main
      MultiSource/Benchmarks/Olden/voronoi/voronoi
      MultiSource/Benchmarks/mafft/pairlocalalign
      MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
      SingleSource/Benchmarks/CoyoteBench/almabench
      SingleSource/Benchmarks/Misc/matmul_f64_4x4

 - The lowering currently falls back to using Altivec instructions far more
   than it should. Worse, there are some things that are scalarized through the
   stack that shouldn't be.

 - A lot of unnecessary copies make it past the optimizers, and this needs to
   be fixed.

 - Many more regression tests are needed.

Normally, I'd fix these things prior to committing, but there are some
students and other contributors who would like to work this, and so it makes
sense to move this development process upstream where it can be subject to the
regular code-review procedures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203768 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 07:58:58 +00:00
Hal Finkel
79c15b23c9 [TableGen] Optionally forbid overlap between named and positional operands
There are currently two schemes for mapping instruction operands to
instruction-format variables for generating the instruction encoders and
decoders for the assembler and disassembler respectively: a) to map by name and
b) to map by position.

In the long run, we'd like to remove the position-based scheme and use only
name-based mapping. Unfortunately, the name-based scheme currently cannot deal
with complex operands (those with suboperands), and so we currently must use
the position-based scheme for those. On the other hand, the position-based
scheme cannot deal with (register) variables that are split into multiple
ranges. An upcoming commit to the PowerPC backend (adding VSX support) will
require this capability. While we could teach the position-based scheme to
handle that, since we'd like to move away from the position-based mapping
generally, it seems silly to teach it new tricks now. What makes more sense is
to allow for partial transitioning: use the name-based mapping when possible,
and only use the position-based scheme when necessary.

Now the problem is that mixing the two sensibly was not possible: the
position-based mapping would map based on position, but would not skip those
variables that were mapped by name. Instead, the two sets of assignments would
overlap. However, I cannot currently change the current behavior, because there
are some backends that rely on it [I think mistakenly, but I'll send a message
to llvmdev about that]. So I've added a new TableGen bit variable:
noNamedPositionallyEncodedOperands, that can be used to cause the
position-based mapping to skip variables mapped by name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203767 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 07:57:54 +00:00
Saleem Abdulrasool
7c801675f8 ARM: ignore unused variable to fix -Wunused-variable builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203765 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 07:15:45 +00:00
Saleem Abdulrasool
0ed4ef85a8 ARM: support emission of complex SO expressions
Support to the IAS was added to actually parse and handle the complex SO
expressions.  However, the object file lowering was not updated to compensate
for the fact that the shift operand may be an absolute expression.

When trying to assemble to an object file, the lowering would fail while
succeeding when emitting purely assembly.  Add an appropriate test.

The test case is inspired by the test case provided by Jiangning Liu who also
brought the issue to light.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203762 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 07:02:41 +00:00
Adam Nemet
a65ca9dcf0 [X86] Add peephole for masked rotate amount
Extend what's currently done for shift because the HW performs this masking
implicitly:

   (rotl:i32 x, (and y, 31)) -> (rotl:i32 x, y)

I use the newly factored out multiclass that was only supporting shifts so
far.

For testing I extended my testcase for the new rotation idiom.

<rdar://problem/15295856>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203718 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 21:20:55 +00:00
Roman Divacky
060c0eb1d2 Allow exclamation and tilde to be parsed as a part of the ppc asm operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203699 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 19:25:57 +00:00
Matt Arsenault
054f4eccd2 R600: Fix trunc store from i64 to i1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203695 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 18:45:52 +00:00
Adam Nemet
77d21e8550 [X86] Refactor peepholes for masked shift amount into a multiclass
The peephole (shift x, (and y, 31)) -> (shift x, y) is repeated for each
integer type and each shift variant.

To improve this a new multiclass is added that covers all integer types.  The
shift patterns are now instantiated from this.  I am planning to add new
instances for rotates as well.

No functional change intended:

  * test/CodeGen/X86/shift-and.ll provides coverage

  * Compared the expanded tablegen output and matched up the defs for these
    Pat<>s before and after

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203685 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 18:02:33 +00:00
Quentin Colombet
a6b6d52299 [X86] Set the scheduling resources of some of the FPStack instructions.
This is related to <rdar://problem/15607571>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203682 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 17:33:42 +00:00
Rafael Espindola
3b8cc2299b Try harder to evaluate expressions when printing assembly.
When printing assembly we don't have a Layout object, but we can still
try to fold some constants.

Testcase by Ulrich Weigand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203677 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 16:55:59 +00:00
Hans Wennborg
72b4cbf3ed Add comment pointing to the binutils bugzilla entry
This is a follow-up to r203635 as suggested by Rafael.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203670 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 16:14:23 +00:00
Will Schmidt
3d37204ca6 Update the datalayout string for ppc64LE.
Update the datalayout string for ppc64LE.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203664 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 14:59:17 +00:00
Daniel Sanders
58b6bfeb22 [mips][fp64] Add an implicit def to MTHC1 claiming that it reads the lower 32-bits of 64-bit FPR
Summary:
This is a white lie to workaround a widespread bug in the -mfp64
implementation.

The problem is that none of the 32-bit fpu ops mention the fact that they
clobber the upper 32-bits of the 64-bit FPR. This allows MTHC1 to be
scheduled on the wrong side of most 32-bit FPU ops, particularly MTC1.
Fixing that requires a major overhaul of the FPU implementation which can't
be done right now due to time constraints.

The testcase is SingleSource/Benchmarks/Misc/oourafft.c when given
TARGET_CFLAGS='-mips32r2 mfp64 -mmsa'.

Also correct the comment added in r203464 to indicate that two
instructions were affected.

Reviewers: matheusalmeida, jacksprat

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3029

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203659 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 13:35:43 +00:00
Daniel Sanders
fe6bd52bf2 [mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern.
Summary:
Correct the match patterns and the lowerings that made the CodeGen tests pass despite the mistakes.

The original testcase that discovered the problem was SingleSource/UnitTests/SignlessType/factor.c in test-suite.
During review, we also found that some of the existing CodeGen tests were incorrect and fixed them:
* bitwise.ll: In bsel_v16i8 the IfSet/IfClear were reversed because bsel and bmnz have different operand orders and the test didn't correctly account for this. bmnz goes 'IfClear, IfSet, CondMask', while bsel goes 'CondMask, IfClear, IfSet'.
* vec.ll: In the cases where a bsel is emitted as a bmnz (they are the same operation with a different input tied to the result) the operands were in the wrong order.
* compare.ll and compare_float.ll: The bsel operand order was correct for a greater-than comparison, but a greater-than comparison instruction doesn't exist. Lowering this operation inverts the condition so the IfSet/IfClear need to be swapped to match.

The differences between BSEL, BMNZ, and BMZ and how they map to/from vselect are rather confusing. I've therefore added a note to MSA.txt to explain this in a single place in addition to the comments that explain each case.

Reviewers: matheusalmeida, jacksprat

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3028

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203657 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 11:54:00 +00:00
Tim Northover
d4517fa24d ARM: correct Dwarf output for non-contiguous VFP saves.
When the list of VFP registers to be saved was non-contiguous (so multiple
vpush/vpop instructions were needed) these were being ordered oddly, as in:
    vpush {d8, d9}
    vpush {d11}

This led to the layout in memory being [d11, d8, d9] which is ugly and doesn't
match the CFI_INSTRUCTIONs we're generating either (so Dwarf info would be
broken).

This switches the order of vpush/vpop (in both prologue and epilogue,
obviously) so that the Dwarf locations are correct again.

rdar://problem/16264856

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203655 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 11:29:23 +00:00
Patrik Hagglund
792a1d7191 Replace '#include ValueTypes.h' with forward declarations.
In some cases the include is pushed "downstream" (or removed if
unused).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203644 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 08:00:24 +00:00
Hans Wennborg
e03daa01f6 [ARM] Use DWARF register numbers for CFI directives in ELF assembly
It seems gas can't handle CFI directives with VFP register names ("d12", etc.).
This broke us trying to build Chromium for Android after 201423.

A gas bug has been filed: https://sourceware.org/bugzilla/show_bug.cgi?id=16694

compnerd suggested making this conditional on whether we're using the integrated
assembler or not. I'll look into that in a follow-up patch.

Differential Revision: http://llvm-reviews.chandlerc.com/D3049

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203635 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 03:52:34 +00:00
Sasa Stankovic
ff73a2bf86 [mips] Implement NaCl sandboxing of function calls:
* Add masking instructions before indirect calls (in MC layer).
  * Align call + branch delay to the bundle end (in MC layer).

Differential Revision: http://llvm-reviews.chandlerc.com/D3032


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203606 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 21:23:40 +00:00
Rafael Espindola
d1742f6136 Simplify a really complicated check for Arch == X86_64.
The function hasReliableSymbolDifference had exactly one use in the MachO
writer. It is also only true for X86_64. In fact, the comments refers to
"Darwin x86_64" and everything else, so this makes the code match the
comment.

If this is to be abstracted again, it should be a property of
TargetObjectWriter, like useAggressiveSymbolFolding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203605 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 21:22:57 +00:00
Owen Anderson
7532403f2c Range-ify a loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203590 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 17:37:48 +00:00
Hans Wennborg
1332459dbb X86: Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059)
This fixes the bug where we would bitcast the 64-bit floating point result
of cmpneqsd to a 64-bit integer even on 32-bit targets.

Differential Revision: http://llvm-reviews.chandlerc.com/D3009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203581 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 15:49:24 +00:00
Saleem Abdulrasool
90d0ed297f ARM: honour -f{no-,}optimize-sibling-calls
Use the options in the ARMISelLowering to control whether tail calls are
optimised or not.  Previously, this option was entirely ignored on the ARM
target and only honoured on x86.

This option is mostly useful in profiling scenarios.  The default remains that
tail call optimisations will be applied.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203577 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 15:09:54 +00:00
Saleem Abdulrasool
2b42ff6fdb ARM: remove ancient -arm-tail-calls option
This option is from 2010, designed to work around a linker issue on Darwin for
ARM.  According to grosbach this is no longer an issue and this option can
safely be removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203576 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 15:09:49 +00:00
Saleem Abdulrasool
cde1f2eae2 ARM: enable tail call optimisation on Thumb 2
Tail call optimisation was previously disabled on all targets other than
iOS5.0+.  This enables the tail call optimisation on all Thumb 2 capable
platforms.

The test adjustments are to remove the IR hint "tail" to function invocation.
The tests were designed assuming that tail call optimisations would not kick in
which no longer holds true.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203575 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 15:09:44 +00:00
Tim Northover
90b25eaef2 ARM: simplify EmitAtomicBinary64
ATOMIC_STORE operations always get here as a lowered ATOMIC_SWAP, so there's no
need for any code to handle them specially.

There should be no functionality change so no tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203567 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 13:19:55 +00:00
Tim Northover
ca396e391e IR: add a second ordering operand to cmpxhg for failure
The syntax for "cmpxchg" should now look something like:

	cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic

where the second ordering argument gives the required semantics in the case
that no exchange takes place. It should be no stronger than the first ordering
constraint and cannot be either "release" or "acq_rel" (since no store will
have taken place).

rdar://problem/15996804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203559 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 10:48:52 +00:00
Matt Arsenault
0e5b4860b5 R600: Calculate store mask instead of using switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203527 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 01:38:53 +00:00
Jim Grosbach
7a37166a7a X86: Enable ISel of 16-bit MOVBE instructions.
When the MOVBE instructions are available, use them for 16-bit endian
swapping as well as for 32 and 64 bit.

The patterns were already present on the instructions, but weren't being
matched because the operation was unconditionally marked to 'Expand.'
Change that to be conditional on whether the MOVBE instructions are
available. Use 'rolw' to implement the in-register version (32 and 64
bit have the dedicated 'bswap' instruction for that).

Patch by Louis Gerbarg <lgg@apple.com>.

rdar://15479984

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203524 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 00:44:14 +00:00
Matt Arsenault
bea18e3849 Remove incomplete comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203518 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 00:01:37 +00:00
Matt Arsenault
6cf9da3d85 Move trivial getter into header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203517 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 00:01:34 +00:00
Matt Arsenault
cc1240ee1b Use .data() instead of &x[0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203516 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 00:01:31 +00:00
Matt Arsenault
60616b61dc Fix indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203515 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 00:01:27 +00:00
Sasa Stankovic
754aaee387 [mips] Implement NaCl sandboxing of loads, stores and SP changes:
* Add masking instructions before loads and stores (in MC layer).
  * Add masking instructions after SP changes (in MC layer).
  * Forbid loads, stores and SP changes in delay slots (in MI layer).

Differential Revision: http://llvm-reviews.chandlerc.com/D2904


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203484 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-10 20:34:23 +00:00
Eli Bendersky
c32c110b90 Make sure NVPTX doesn't emit symbol names that aren't valid in PTX.
NVPTX, like the other backends, relies on generic symbol name sanitizing done by
MCSymbol. However, the ptxas assembler is more stringent and disallows some
additional characters in symbol names.

See PR19099 for more details.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203483 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-10 20:05:42 +00:00
Reed Kotler
017bc0fca6 Fix regression with -O0 for mips .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203469 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-10 16:31:25 +00:00
Daniel Sanders
e1820a6a4e [mips][fp64] Add an implicit def to MFHC1 claiming that it reads the lower 32-bits of 64-bit FPR
Summary:
This is a white lie to workaround a widespread bug in the -mfp64
implementation.

The problem is that none of the 32-bit fpu ops mention the fact that they
clobber the upper 32-bits of the 64-bit FPR. This allows MFHC1 to be
scheduled on the wrong side of most 32-bit FPU ops. Fixing that requires a
major overhaul of the FPU implementation which can't be done right now due to
time constraints.

MFHC1 is one of two affected instructions. These instructions are the only
FPU instructions that don't read or write the lower 32-bits. We therefore
pretend that it reads the bottom 32-bits to artificially create a dependency and
prevent the scheduler changing the behaviour of the code.
The other instruction is MTHC1 which will be fixed once I've have found a failing
test case for it. 

The testcase is test-suite/SingleSource/UnitTests/Vector/simple.c when
given TARGET_CFLAGS="-mips32r2 -mfp64 -mmsa".

Reviewers: jacksprat, matheusalmeida

Reviewed By: jacksprat

Differential Revision: http://llvm-reviews.chandlerc.com/D2966

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203464 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-10 15:01:57 +00:00
Matheus Almeida
ffb6f6ed2a [mips] Assembly parser must invoke the target streamer to handle .set reorder macro.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203459 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-10 13:21:10 +00:00
Tim Northover
8ca089df49 AArch64: fix LowerCONCAT_VECTORS for new CodeGen.
The function was making too many assumptions about its input:

1. The NEON_VDUP optimisation was far too aggressive, assuming (I
think) that the input would always be BUILD_VECTOR.

2. We were treating most unknown concats as legal (by returning Op
rather than SDValue()). I think only concats of pairs of vectors are
actually legal.

http://llvm.org/PR19094

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203450 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-10 09:34:07 +00:00
Craig Topper
3b89e528c4 [C++11] Remove 'virtual' keyword from methods marked with 'override' keyword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203444 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-10 05:29:18 +00:00
Chandler Carruth
292fcee823 [AArch64] Fix a use of uninitialized memory introduced in r203125,
and caught by the MSan bootstrap build bot. This should hopefully get
the bot green at long last.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203441 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-10 03:52:47 +00:00
Craig Topper
984084aa05 De-virtualize a method since it doesn't override anything and isn't overridden itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203440 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-10 03:22:59 +00:00
Craig Topper
3d3e407e5f [C++11] Add 'override' keyword to virtual methods that override their base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203439 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-10 03:19:03 +00:00
Chandler Carruth
436906ab3c [TTI] There is actually no realistic way to pop TTI implementations off
the stack of the analysis group because they are all immutable passes.
This is made clear by Craig's recent work to use override
systematically -- we weren't overriding anything for 'finalizePass'
because there is no such thing.

This is kind of a lame restriction on the API -- we can no longer push
and pop things, we just set up the stack and run. However, I'm not
invested in building some better solution on top of the existing
(terrifying) immutable pass and legacy pass manager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203437 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-10 02:45:14 +00:00
Craig Topper
d11898db4c [C++11] Add 'override' keyword to virtual methods that override their base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203433 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-10 02:09:33 +00:00