Commit Graph

74385 Commits

Author SHA1 Message Date
Zoran Jovanovic
d67cd80220 [mips][micromips] Implement SWM32 and LWM32 instructions
Differential Revision: http://reviews.llvm.org/D5519


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222367 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 16:44:02 +00:00
Suyog Sarda
ca72befdb5 Vectorize a reduction chain feeding into a 'return' statement.
e.x 
return (a[0]+b[0]) + (a[1]+b[1])

Differential Revision: http://reviews.llvm.org/D6227



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222364 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 16:07:38 +00:00
Jozef Kolek
9fece51399 [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.
Differential Revision: http://reviews.llvm.org/D6169


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222355 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 13:37:51 +00:00
Arnaud A. de Grandmaison
beeec3231e Fix tail recursion elimination
When the BasicBlock containing the return instrution has a PHI with 2
incoming values, FoldReturnIntoUncondBranch will remove the no longer
used incoming value and remove the no longer needed phi as well. This
leaves us with a BB that no longer has a PHI, but the subsequent call
to FoldReturnIntoUncondBranch from FoldReturnAndProcessPred will not
remove the return instruction (which still uses the result of the call
instruction). This prevents EliminateRecursiveTailCall to remove
the value, as it is still being used in a basicblock which has no
predecessors.

The basicblock can not be erased on the spot, because its iterator is
still being used in runTRE.

This issue was exposed when removing the threshold on size for lifetime
marker insertion for named temporaries in clang. The testcase is a much
reduced version of peelOffOuterExpr(const Expr*, const ExplodedNode *)
from clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222354 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 13:32:51 +00:00
Jozef Kolek
e4e84b22fe [mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2.
Differential Revision: http://reviews.llvm.org/D5800


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222352 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 13:23:58 +00:00
Jozef Kolek
5c6c7e3295 [mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction.
Differential Revision: http://reviews.llvm.org/D5799


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222351 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 13:11:09 +00:00
Jozef Kolek
43ae00e4e0 [mips][microMIPS] Implement LWXS instruction.
Differential Revision: http://reviews.llvm.org/D5407


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222348 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 11:39:12 +00:00
Jozef Kolek
baf97d8987 [mips][microMIPS] Implement SDBBP and RDHWR instructions.
Differential Revision: http://reviews.llvm.org/D5240


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222347 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 11:25:50 +00:00
Simon Pilgrim
a6943fff90 [X86][SSE] pslldq/psrldq byte shifts/rotation for SSE2
This patch builds on http://reviews.llvm.org/D5598 to perform byte rotation shuffles (lowerVectorShuffleAsByteRotate) on pre-SSSE3 (palignr) targets - pre-SSSE3 is only enabled on i8 and i16 vector targets where it is a more definite performance gain.

I've also added a separate byte shift shuffle (lowerVectorShuffleAsByteShift) that makes use of the ability of the SLLDQ/SRLDQ instructions to implicitly shift in zero bytes to avoid the need to create a zero register if we had used palignr.

Differential Revision: http://reviews.llvm.org/D5699



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222340 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 10:06:49 +00:00
David Majnemer
f47d325eec AliasSetTracker: UnknownInsts should contribute to the refcount
AliasSetTracker::addUnknown may create an AliasSet devoid of pointers
just to contain an instruction if no suitable AliasSet already exists.
It will then AliasSet::addUnknownInst and we will be done.

However, it's possible for addUnknown to choose an existing AliasSet to
addUnknownInst.
If this were to occur, we are in a bit of a pickle: removing pointers
from the AliasSet can cause the entire AliasSet to become destroyed,
taking our unknown instructions out with them.

Instead, keep track whether or not our AliasSet has any unknown
instructions.

This fixes PR21582.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222338 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 09:41:05 +00:00
David Blaikie
5401ba7099 Update SetVector to rely on the underlying set's insert to return a pair<iterator, bool>
This is to be consistent with StringSet and ultimately with the standard
library's associative container insert function.

This lead to updating SmallSet::insert to return pair<iterator, bool>,
and then to update SmallPtrSet::insert to return pair<iterator, bool>,
and then to update all the existing users of those functions...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222334 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 07:49:26 +00:00
Hao Liu
0e8675a621 [AArch64] Disable useAA for Cortex-A57.
Using AA during CodeGen is very useful for in-order cores. It is less useful for ooo cores. Also I find
enabling useAA for Cortex-A57 may generate worse code for some test cases. If useAA in codegen is improved 
and benefical for ooo cores, we can enable it again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222333 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 06:48:56 +00:00
Hao Liu
8db9fbf7cd [AArch64] Enable SeparateConstOffsetFromGEP, EarlyCSE and LICM passes on AArch64 backend.
SeparateConstOffsetFromGEP can gives more optimizaiton opportunities related to GEPs, which benefits EarlyCSE
and LICM. By enabling these passes we can have better address calculations and generate a better addressing
mode. Some SPEC 2006 benchmarks (astar, gobmk, namd) have obvious improvements on Cortex-A57.

Reviewed in http://reviews.llvm.org/D5864.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222331 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 06:39:53 +00:00
Hao Liu
eb52f383c2 [SeparateConstOffsetFromGEP] Allow SeparateConstOffsetFromGEP pass to lower GEPs.
If LowerGEP is enabled, it can lower a GEP with multiple indices into GEPs with a single index
or arithmetic operations. Lowering GEPs can always extract structure indices. Lowering GEPs can
also give use more optimization opportunities. It can benefit passes like CSE, LICM and CGP.

Reviewed in http://reviews.llvm.org/D5864


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222328 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 06:24:44 +00:00
David Blaikie
1d4f28c6bc Remove StringMap::GetOrCreateValue in favor of StringMap::insert
Having two ways to do this doesn't seem terribly helpful and
consistently using the insert version (which we already has) seems like
it'll make the code easier to understand to anyone working with standard
data structures. (I also updated many references to the Entry's
key and value to use first() and second instead of getKey{Data,Length,}
and get/setValue - for similar consistency)

Also removes the GetOrCreateValue functions so there's less surface area
to StringMap to fix/improve/change/accommodate move semantics, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222319 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 05:49:42 +00:00
Rui Ueyama
3977e2f696 llvm-readobj: fix off-by-one error in COFFDumper
It printed out base relocation table header as table entry.
This patch also makes llvm-readobj to not skip ABSOLUTE entries
becuase it was confusing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222299 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 02:07:10 +00:00
Weiming Zhao
d8e31c73cd [Aarch64] Customer lowering of CTPOP to SIMD should check for NEON availability
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222292 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 00:29:14 +00:00
Kostya Serebryany
0dd5e22d89 [asan] add experimental basic-block tracing to asan-coverage; also fix -fsanitize-coverage=3 which was broken by r221718
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222290 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 00:22:58 +00:00
Rui Ueyama
6272b8c4be llvm-readobj: teach it how to dump COFF base relocation table
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222289 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 00:18:07 +00:00
Kostya Serebryany
f82e60f03d Introduce llvm::SplitAllCriticalEdges
Summary:
move the code from BreakCriticalEdges::runOnFunction()
into a separate utility function llvm::SplitAllCriticalEdges()
so that it can be used independently.
No functionality change intended.

Test Plan: check-llvm

Reviewers: nlewycky

Reviewed By: nlewycky

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6313

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222288 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 00:17:31 +00:00
Manman Ren
2b82868de5 Revert r222039 because of bot failure.
http://lab.llvm.org:8080/green/job/clang-Rlto_master/298/
Hopefully, bot will be green. If not, we will re-submit the commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222287 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 00:13:26 +00:00
Matt Arsenault
1bd96c574c R600/SI: Implement areMemAccessesTriviallyDisjoint
This partially makes up for not having address spaces
used for alias analysis in some simple cases.

This is not yet enabled by default so shouldn't change anything yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222286 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 00:01:31 +00:00
Matt Arsenault
b556213712 R600/SI: Set hasSideEffects = 0 on load and store instructions.
Assuming unmodeled side effects interferes with some scheduling
opportunities.

Don't put it in the base class of DS instructions since there
are a few weird effecting, non load/store instructions there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222285 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 23:57:33 +00:00
Simon Pilgrim
e6d1a2625f [X86][AVX] 256-bit vector stack unaligned load/stores identification
Under many circumstances the stack is not 32-byte aligned, resulting in the use of the vmovups/vmovupd/vmovdqu instructions when inserting ymm reloads/spills.

This minor patch adds these instructions to the isFrameLoadOpcode/isFrameStoreOpcode helpers so that they can be correctly identified and not be treated as folded reloads/spills.

This has also been noticed by http://llvm.org/bugs/show_bug.cgi?id=18846 where it was causing redundant spills - I've added a reduced test case at test/CodeGen/X86/pr18846.ll

Differential Revision: http://reviews.llvm.org/D6252



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222281 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 23:38:19 +00:00
Colin LeMahieu
642bb08576 [Hexagon] Adding A2_and instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222274 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 22:45:47 +00:00
Chad Rosier
32dc2de667 [FastISel][AArch64] Also allow folding of sign-/zero-extend and arithmetic
shift-right for booleans (i1).

Arithmetic shift-right immediate with sign-/zero-extensions also works for
boolean values.  Update the assert and the test cases to reflect that fact.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222272 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 22:41:49 +00:00
Chad Rosier
5e3288f85b [FastISel][AArch64] Also allow folding of sign-/zero-extend and logical
shift-right for booleans (i1).

Logical shift-right immediate with sign-/zero-extensions also works for boolean
values.  Update the assert and the test cases to reflect that fact.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222270 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 22:38:42 +00:00
David Majnemer
643bef9333 InstCombine: Fix another infinite loop caused by visitFPTrunc
We would attempt to replace an frem's operand with the same operand.
This would cause InstCombine to think real work was done, causing
InstCombine to enter an infinite loop.

This fixes the second part of PR21576.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222265 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 22:06:45 +00:00
Colin LeMahieu
ed37b1e2d0 [Hexagon] Adding A2_sub instruction
Renaming test files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222263 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 21:51:51 +00:00
David Majnemer
063e54286c Revert "Revert r222040 because of bot failure."
This reverts commit r222203, reverting r222040 didn't end up turning the
bot green.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222261 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 21:30:02 +00:00
Juergen Ributzka
52e0f75f82 [FastISel][AArch64] Follow-up fix for "Fix shift-immediate emission for "zero" shifts."
Shifts also perform sign-/zero-extends to larger types, which requires us to emit
an integer extend instead of a simple COPY.

Related to PR21594.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222257 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 21:20:17 +00:00
Matt Arsenault
a140448780 R600/SI: Move SIFixSGPRCopies to inst selector passes
This should expose more of the actually used VALU
instructions to the machine optimization passes.

This also should help getting i1 handling into a better state.
For not entirly understood reasons, this fixes the split-scalar-i64-add.ll
test where a 64-bit add would only partially be moved to the VALU
resulting in use of undefined VCC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222256 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 21:06:58 +00:00
Juergen Ributzka
50fa2ff5d2 [AArch64] Don't optimize all compare instructions.
"optimizeCompareInstr" converts compares (cmp/cmn) into plain sub/add
instructions when the flags are not used anymore. This conversion is valid for
most instructions, but not all. Some instructions that don't set the flags
(e.g. sub with immediate) can set the SP, whereas the flag setting version uses
the same encoding for the "zero" register.

Update the code to also check for the return register before performing the
optimization to make sure that a cmp doesn't suddenly turn into a sub that sets
the stack pointer.

I don't have a test case for this, because it isn't easy to trigger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222255 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 21:02:40 +00:00
Owen Anderson
b39e517168 Fix an incorrect chain operand when expanding INSERT_VECTOR operations through the stack.
Patch by Daniil Troshkov!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 20:50:19 +00:00
Tom Stellard
891e9e7869 R600/SI: Make sure resource descriptors are always stored in SGPRs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222253 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 20:39:39 +00:00
Colin LeMahieu
b7927f100d [Hexagon] Converting from ADD_rr to A2_add which has encoding bits.
Adding test to show correct instruction selection and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222249 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 20:28:11 +00:00
Chad Rosier
3980c542e6 [Reassociate] Rename local variable to not use same name as a member
variable. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222248 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 20:21:54 +00:00
Juergen Ributzka
8b62d78689 [FastISel][AArch64] Fix shift-immediate emission for "zero" shifts.
This change emits a COPY for a shift-immediate with a "zero" shift value.
This fixes PR21594 where we emitted a shift instruction with an incorrect
immediate operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222247 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 19:58:59 +00:00
Jozef Kolek
c8ec320371 Test commit to verify that commit access works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222244 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 19:20:34 +00:00
Philip Reames
0814bd85dd Tweak EarlyCSE to recognize series of dead stores
EarlyCSE is giving up on the current instruction immediately when it recognizes that the current instruction makes a previous store trivially dead. There's no reason to do this. Once the previous store has been deleted, it's perfectly legal to remember the value of the current store (for value forwarding) and the fact the store occurred (it could be dead too!).

Reviewed by: Hal
Differential Revision: http://reviews.llvm.org/D6301



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222241 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 17:46:32 +00:00
David Majnemer
0ede3a2ae5 InstCombine: Fold away tautological masked compares
It is impossible for (x & INT_MAX) == 0 && x == INT_MAX to ever be true.

While this sort of reasoning should normally live in InstSimplify,
the machinery that derives this result is not trivial to split out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222230 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 09:31:41 +00:00
David Majnemer
2c906a4607 InstCombine: Clean up foldLogOpOfMaskedICmps
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222229 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 09:31:36 +00:00
Frederic Riss
60a8349a7d Allow DwarfCompileUnit::constructImportedEntityDIE to instanciate a GlobalVariable DIE.
Usually global variables are in a retain list and instanciated before
any call to constructImportedEntityDIE is made. This isn't true for
forward declarations though.
The testcase for this change is generated by a clang patched to emit
such forward declarations (patch at http://reviews.llvm.org/D6173
which will land soon). The updated testcase tests more than just
global variables, it now tests every type of 'using' clause we
support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222217 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 02:46:11 +00:00
Hans Wennborg
9ba744b089 SimplifyCFG: Range'ify some for-loops. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222215 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 02:37:11 +00:00
David Majnemer
1ade0f0faa IndVarSimplify: Allow LFTR to fire more often
I added a pessimization in r217102 to prevent miscompiles when the
incremented induction variable was used in a comparison; it would be
poison.

Try to use the incremented induction variable more often when we can be
sure that the increment won't end in poison.

Differential Revision: http://reviews.llvm.org/D6222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222213 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 02:20:58 +00:00
Duncan P. N. Exon Smith
5d8a792eac IR: Sink MDNode::Hash down to GenericMDNode::Hash
Part of PR21532.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222212 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 02:20:29 +00:00
Duncan P. N. Exon Smith
023c72e64a IR: Move MDNode operands from the back to the front
Having the operands at the back prevents subclasses from safely adding
fields.  Move them to the front.

Instead of replicating the custom `malloc()`, `free()` and `DestroyFlag`
logic that was there before, overload `new` and `delete`.

I added calls to a new `GenericMDNode::dropAllReferences()` in
`LLVMContextImpl::~LLVMContextImpl()`.  There's a maze of callbacks
happening during teardown, and this resolves them before we enter
the destructors.

Part of PR21532.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222211 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 01:56:14 +00:00
Michael J. Spencer
182856d70c Fix covered switch warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222209 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 01:26:46 +00:00
Michael J. Spencer
b9f39bcc82 Support ELF files of unknown type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222208 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 01:14:25 +00:00
Duncan P. N. Exon Smith
2c38b004d9 IR: Split MDNode into GenericMDNode and MDNodeFwdDecl
Split `MDNode` into two classes:

  - `GenericMDNode`, which is uniquable (and for now, always starts
    uniqued).  Once `Metadata` is split from the `Value` hierarchy, this
    class will lose the ability to RAUW itself.

  - `MDNodeFwdDecl`, which is used for the "temporary" interface, is
    never uniqued, and isn't managed by `LLVMContext` at all.

I've left most of the guts in `MDNode` for now, but I'll incrementally
move things to the right places (or delete the functionality, as
appropriate).

Part of PR21532.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222205 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 00:37:17 +00:00