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4 Commits

Author SHA1 Message Date
Benjamin Kramer
4dc478308f When lowering an inreg sext first shift left, then right arithmetically. 
Shifting right two times will only yield zero. Should fix
SingleSource/UnitTests/SignlessTypes/factor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172322 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-12 19:06:44 +00:00
Nadav Rotem
66de2af815 PPC: Implement efficient lowering of sign_extend_inreg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172269 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-11 22:57:48 +00:00
Bill Schmidt
527388dea5 This patch is in preparation for adding medium code model support to the 
PPC64 target.  The five tests modified herein test code generation that is
sensitive to the code model selected.  So I've added -code-model=small to
the RUN commands for each.

Since small code model is the default, this has no effect for now; but this
prepares us for eventually changing the default to medium code model for PPC64.

Test changes verified with small and medium code model as default on
powerpc64-unknown-linux-gnu.  All tests continue to pass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167999 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 23:23:27 +00:00
Adhemerval Zanella
cfe09ed28d [PATCH] PowerPC: Expand load extend vector operations 
This patch expands the SEXTLOAD, ZEXTLOAD, and EXTLOAD operations for
vector types when altivec is enabled.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167386 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-05 17:15:56 +00:00