Commit Graph

13 Commits

Author SHA1 Message Date
Duraid Madina
63bbed536c add the popcount instruction and support this in the isel
the primary user of this will probably end up being find-first-set-bit/find-
last-set-bit, which i'll get around to...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21860 91177308-0d34-0410-b5e6-96231b3b80d8
2005-05-11 05:16:09 +00:00
Duraid Madina
1ce0c015ad print negative 64 bit immediates as negative numbers, makes things a little
easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21300 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-14 10:08:01 +00:00
Duraid Madina
ed09502a0b * add the shladd instruction
* fold left shifts of 1, 2, 3 or 4 bits into adds

  This doesn't save much now, but should get a serious workout once
  multiplies by constants get converted to shift/add/sub sequences.
  Hold on! :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21282 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13 06:12:04 +00:00
Chris Lattner
ea6f770fb0 Make sure to realize that calls use their argument regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21248 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12 15:12:19 +00:00
Duraid Madina
5ef2ec9929 assorted fixes:
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
  * fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
  * fix nasty thinko - didn't use two-address form of conditional add
    for extending bools to integers, so occasionally there would be
    garbage in the result. it's amazing how often zeros are just
    sitting around in registers ;) - this should fix a bunch of tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21221 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-11 05:55:56 +00:00
Duraid Madina
6dcceb5ecb fix bogus division-by-power-of-2 (was wrong for negative input, adds extr insn)
fix hack in division (clean up frcpa instruction)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21153 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-08 10:01:48 +00:00
Duraid Madina
18c0c6bcc4 add immediate forms of add, sub, shift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21129 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-07 12:32:24 +00:00
Duraid Madina
b366a02ff2 add fms instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21112 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 09:54:09 +00:00
Duraid Madina
09c61b9c19 add implicit use op
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21074 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 04:50:57 +00:00
Duraid Madina
5c156b7473 add fnegabs op
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21022 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 10:06:27 +00:00
Duraid Madina
a7ee8b8f04 add support FNEG and FABS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21012 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 05:18:38 +00:00
Duraid Madina
291e1266c1 add what we need to fudge a 'floating point conditional move', this is
used to get FP div-by-zero working properly (shunt the right answer
depending on how frcpa sets its predicate output)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20954 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-31 07:32:32 +00:00
Duraid Madina
9b9d45f60e and so it begins...
PHASE 1: write instruction selector
PHASE 2: ???
PHASE 3: profit!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20652 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-17 18:17:03 +00:00