Commit Graph

18962 Commits

Author SHA1 Message Date
Richard Osborne
db51e31527 [XCore] Give test more generic name.
I intend to extend the test with more offset folding checks


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179620 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16 19:56:55 +00:00
Richard Osborne
b509b65240 [XCore] Convert a couple of tests to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179619 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16 19:41:19 +00:00
Logan Chien
532854d7ab Implement ARM unwind opcode assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179591 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16 12:02:21 +00:00
Alexey Samsonov
0eaa6f675c llvm-objdump: Don't print contents of BSS sections: it makes no sense and crashes llvm-objdump on relocated objects with large bss
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179589 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16 10:53:11 +00:00
Hans Wennborg
a121e24c54 simplifycfg: Fix integer overflow converting switch into icmp.
If a switch instruction has a case for every possible value of its type,
with the same successor, SimplifyCFG would replace it with an icmp ult,
but the computation of the bound overflows in that case, which inverts
the test.

Patch by Jed Davis!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179587 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16 08:35:36 +00:00
Jakob Stoklund Olesen
ad36608499 Add 64-bit multiply and divide instructions for SPARC v9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179582 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16 02:57:02 +00:00
Jim Grosbach
d0132ba722 ARM: Add VACLT and VACLE assembly aliases.
These are aliases for VACGT and VACGE, respectively, with the source
operands reversed.

rdar://13638090

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179575 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 22:42:50 +00:00
Bill Wendling
23e00ae631 We are not able to bitcast a pointer to an integral value.
Two return types are not equivalent if one is a pointer and the other is an
integral. This is because we cannot bitcast a pointer to an integral value.
PR15185


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 22:33:50 +00:00
Jack Carter
b8145e3881 Mips assembler: Explicit floating point condition register recognition.
This patch allows the assembler to recognize $fcc0 
as a valid register for conditional move instructions. 

Corresponding test cases have been added.

Contributer: Vladimir Medic



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 22:21:55 +00:00
Nadav Rotem
e9a4411db4 SLPVectorizer: Make it a function pass and add code for hoisting the vector-gather sequence out of loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179562 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 22:00:26 +00:00
Tom Stellard
9a256300f8 R600/SI: Emit config values in register value pairs.
Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 17:51:35 +00:00
Tom Stellard
bf1efe6421 R600/SI: Emit configuration value in the .AMDGPU.config ELF section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179545 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 17:51:30 +00:00
Tom Stellard
3a63bf27c5 R600: Emit ELF formatted code rather than raw ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179544 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 17:51:21 +00:00
Tim Northover
d354644eb1 Avoid outputting temporary test file into source tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179532 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 15:49:13 +00:00
Eric Christopher
60d20a81fc Revert "Recommit r179497 after fixing uninitialized variable." until
I can fix the testcases here:

http://lab.llvm.org:8011/builders/clang-native-arm-cortex-a9/builds/6952

This reverts commit r179512 due to testcases specifying triples
that they didn't actually mean and causing failures on other platforms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179513 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 07:31:37 +00:00
Eric Christopher
fdf9624f3c Recommit r179497 after fixing uninitialized variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179512 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 07:07:21 +00:00
Nadav Rotem
09616565dd SLPVectorizer: Add support for vectorizing trees that start at compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179504 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 04:25:27 +00:00
Hal Finkel
fb6fe0aea2 Fix PPC64 CR spill location for callee-saved registers
This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition
registers, the spill location is specified relative to the stack pointer (SP +
8). However, this is not relative to the SP after the new stack frame is
established, but instead relative to the caller's stack pointer (it is stored
into the linkage area of the parent's stack frame).

So, like with the link register, we don't directly spill the CRs with other
callee-saved registers, but just mark them to be spilled during prologue
generation.

In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179500 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 02:07:05 +00:00
Eric Christopher
f1216abf7e Revert "Remove some unused triple and data layout."
This reverts commit r179497 and the accompanying commit as it broke random platforms that aren't osx.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179499 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 23:35:36 +00:00
Eric Christopher
199ff9cdd7 Remove some unused triple and data layout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179498 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 23:32:44 +00:00
Nico Rieck
ef1762b6a1 Use object file specific section type for initial text section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 21:18:36 +00:00
David Majnemer
024d943bca Reorders two transforms that collide with each other
One performs: (X == 13 | X == 14) -> X-13 <u 2
The other: (A == C1 || A == C2) -> (A & ~(C1 ^ C2)) == C1

The problem is that there are certain values of C1 and C2 that
trigger both transforms but the first one blocks out the second,
this generates suboptimal code.

Reordering the transforms should be better in every case and
allows us to do interesting stuff like turn:
  %shr = lshr i32 %X, 4
  %and = and i32 %shr, 15
  %add = add i32 %and, -14
  %tobool = icmp ne i32 %add, 0

into:
  %and = and i32 %X, 240
  %tobool = icmp ne i32 %and, 224


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179493 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 21:15:43 +00:00
Nadav Rotem
687a9dfcb9 Make the command line triple match the module triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179492 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 20:13:05 +00:00
Jakob Stoklund Olesen
d9f88da7b3 Use i32 for all SPARC shift amounts, even in 64-bit mode.
Test case by llvm-stress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179477 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 05:48:50 +00:00
Nadav Rotem
1f098af364 Remove unused function attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 05:47:04 +00:00
Nadav Rotem
ab105ae95f SLPVectorizer: Add support for trees that don't start at binary operators, and add the cost of extracting values from the roots of the tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179475 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 05:15:53 +00:00
Jakob Stoklund Olesen
618eda7a60 Add support for the abs64 SPARC v9 code model.
For when 16 TB just isn't enough.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179474 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 05:10:36 +00:00
Jakob Stoklund Olesen
87ce01739b Add support for the SPARC v9 abs44 code model.
This is the default model for non-PIC 64-bit code. It supports
text+data+bss linked anywhere in the low 16 TB of the address space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179473 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 04:57:51 +00:00
Jakob Stoklund Olesen
2693210656 Also put target flags on SPARC constant pool references.
Constant pool entries are accessed exactly the same way as global
variables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 04:35:16 +00:00
Nadav Rotem
f7eaf29cf7 SLPVectorizer: add initial support for reduction variable vectorization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179470 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 03:22:20 +00:00
Jakob Stoklund Olesen
ef596e1a80 Fix patterns for 64-bit pointers.
This fixes the pic32 code model for SPARC v9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179469 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 01:53:23 +00:00
Jakob Stoklund Olesen
41d59c6130 Define SPARC code models.
Currently, only abs32 and pic32 are implemented. Add a test case for
abs32 with 64-bit code. 64-bit PIC code is currently broken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179463 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13 19:02:23 +00:00
Benjamin Kramer
9cbee63b1a GlobalDCE: Fix an oversight in my last commit that could lead to crashes.
There is a Constant with non-constant operands: blockaddress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179460 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13 16:11:14 +00:00
Benjamin Kramer
8848680ce0 Fix a scalability issue with complex ConstantExprs.
This is basically the same fix in three different places. We use a set to avoid
walking the whole tree of a big ConstantExprs multiple times.

For example: (select cmp, (add big_expr 1), (add big_expr 2))
We don't want to visit big_expr twice here, it may consist of thousands of
nodes.

The testcase exercises this by creating an insanely large ConstantExprs out of
a loop. It's questionable if the optimizer should ever create those, but this
can be triggered with real C code. Fixes PR15714.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179458 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13 12:53:18 +00:00
Hal Finkel
b99c995825 Spill and restore PPC CR registers using the FP when we have one
For functions that need to spill CRs, and have dynamic stack allocations, the
value of the SP during the restore is not what it was during the save, and so
we need to use the FP in these cases (as for all of the other spills and
restores, but the CR restore has a special code path because its reserved slot,
like the link register, is specified directly relative to the adjusted SP).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13 08:09:20 +00:00
Andrew Trick
16de01ec27 Further generalize this scheduler test.
The order of copies depends on queue order, which is not very stable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179456 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13 07:37:27 +00:00
Andrew Trick
4b1a1f34c0 Fix a dislexic regex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179455 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13 07:29:21 +00:00
Andrew Trick
65634fa48d Add a missing REQUIRES: asserts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179453 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13 06:12:46 +00:00
Andrew Trick
4392f0f407 MI-Sched: schedule physreg copies.
The register allocator expects minimal physreg live ranges. Schedule
physreg copies accordingly. This is slightly tricky when they occur in
the middle of the scheduling region. For now, this is handled by
rescheduling the copy when its associated instruction is
scheduled. Eventually we may instead bundle them, but only if we can
preserve the bundles as parallel copies during regalloc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179449 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13 06:07:40 +00:00
Rafael Espindola
da2a2372c6 Finish templating MachObjectFile over endianness.
We are now able to handle big endian macho files in llvm-readobject. Thanks to
David Fang for providing the object files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179440 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13 01:45:40 +00:00
Akira Hatanaka
3d60241c3e [mips] Reapply r179420 and r179421.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179434 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13 00:55:41 +00:00
Akira Hatanaka
d35d5bdfc4 Revert r179420 and r179421.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179422 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 22:40:07 +00:00
Akira Hatanaka
6d224459f4 [mips] Instruction selection patterns for carry-setting and using add
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 22:24:52 +00:00
Akira Hatanaka
9367b8d4f2 [mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179420 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 22:14:24 +00:00
Nadav Rotem
0fda0f3976 Revert r179409 because it caused some warnings and some of the build bots fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179418 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 22:02:26 +00:00
Benjamin Kramer
6ac9278606 InstCombine: Check the operand types before merging fcmp ord & fcmp ord.
Fixes PR15737.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 21:56:23 +00:00
Nadav Rotem
a74f91e44c SLPVectorizer: add support for vectorization of diamond shaped trees. We now perform a preliminary traversal of the graph to collect values with multiple users and check where the users came from.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179414 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 21:16:54 +00:00
Nadav Rotem
9eb366acba CostModel: increase the default cost of supported floating point operations from 1 to two. Fixed a few tests that changes because now the cost of one insert + a vector operation on two doubles is lower than two scalar operations on doubles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 21:15:03 +00:00
Nadav Rotem
affe889d08 Add support for additional vector instructions in the interpreter.
patch by Veselov, Yuri <Yuri.Veselov@intel.com>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179409 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 20:45:20 +00:00
Quentin Colombet
d64ee4455a ARM: Correct printing of pre-indexed operands.
According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes.
The MC disassembler was not obeying this when the offset is 0.
It was producing instructions like: str r0, [r1]!.
Correct syntax is: str r0, [r1, #0]!.

This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used.

Patch by Mihail Popa <Mihail.Popa@arm.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179398 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 18:47:25 +00:00