Chris Lattner
65303d6bd7
Teach tblgen about instruction operands that have multiple MachineInstr
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operands, digging into them to find register values (used on X86). Patch
by Evan Cheng!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24424 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-19 07:05:57 +00:00
Jim Laskey
6cee630070
Allow itineraries to be passed through the Target Machine.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24139 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-01 20:06:59 +00:00
Jeff Cohen
cb366d980a
Keep VC++ happy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24137 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-01 18:04:06 +00:00
Jim Laskey
b5a0c0ee05
Emit itinerary class in instruction info.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24122 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-31 17:16:46 +00:00
Chris Lattner
366080c5e6
Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24074 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-28 22:59:53 +00:00
Chris Lattner
5f89bf0f9d
spell this variable right
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23095 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26 20:42:52 +00:00
Chris Lattner
8b50f9b8dc
Expose a new flag to TargetInstrInfo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23094 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26 20:40:46 +00:00
Chris Lattner
9fdd6e3f50
add a marker at the end of the instruction enum list
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23090 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26 20:17:00 +00:00
Chris Lattner
8d30c23d26
Emit this:
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static const TargetOperandInfo OperandInfo6[] = { { &PPC32::CRRCRegClass }, { 0 }, };
instead of this:
static const TargetOperandInfo OperandInfo6[] = { { PPC32::CRRCRegisterClass }, { 0 }, };
For operand information, which does not require dynamic (startup-time)
initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22931 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 20:29:14 +00:00
Chris Lattner
d5aa3e26bb
Emit real operand info for instructions. This currently works but is bad
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in one way: the generated tables require dynamic initialization for the
register classes. This will be fixed in a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22919 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 18:46:26 +00:00
Chris Lattner
0e384b66a7
For now, just emit empty operand info structures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22910 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 16:57:28 +00:00
Chris Lattner
d98958f4bd
now that all of the targets are clean w.r.t. the number of operands for each
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instruction defined, actually emit this to the InstrInfoDescriptor, which
allows an assert in the machineinstrbuilder to do some checking for us,
and is required by the dag->dag emitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22895 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 00:59:49 +00:00
Chris Lattner
f372ae6ebc
revert this change, which causes breakage, temporarily
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22880 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-18 22:12:31 +00:00
Chris Lattner
a3ac88d8ab
When emitting implicit use/def lists, only emit each unique list once. Though
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LLVM is able to merge identical static const globals, GCC isn't, and this caused
some bloat in the generated data. This has a marginal effect on PPC, shrinking
the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger
reduction.
This should speed up the register allocator as well by reducing the dcache
footprint for this static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22879 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-18 21:36:47 +00:00
Chris Lattner
dcfa353d74
Fill in the numOperands field of the TargetInstrDescriptor struct from the
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.td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22873 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-18 19:45:37 +00:00
Misha Brukman
3da94aec4d
Remove trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21428 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-22 00:00:37 +00:00
Chris Lattner
d648867173
Refactor code for numbering instructions into CodeGenTarget.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19758 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:58:51 +00:00
Chris Lattner
aad75aa1a2
Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19243 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-02 02:29:04 +00:00
Nate Begeman
cdd66b524f
Add support for the isLoad and isStore flags, needed by the instruction scheduler
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16554 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-28 21:01:45 +00:00
Chris Lattner
5b71d3af35
Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16553 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-28 18:38:01 +00:00
Chris Lattner
2c38413b3f
Do not #include files into the llvm namespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15849 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-17 03:08:28 +00:00
Chris Lattner
2d12b2cf75
Instructions no longer need to have names.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15399 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 08:38:17 +00:00
Chris Lattner
ec3524064c
Add, and start using, the CodeGenInstruction class. This class represents
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an instance of the Instruction tablegen class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15385 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 05:04:00 +00:00
Chris Lattner
803a5f6ecb
Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15382 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 04:04:35 +00:00
Chris Lattner
2082ebe8b3
Finegrainify namespacification
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15381 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 03:55:39 +00:00
Chris Lattner
58505994cf
Support new flag
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15355 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-31 02:07:26 +00:00
Brian Gaeke
d0fde30ce8
Put all LLVM code into the llvm namespace, as per bug 109.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9903 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-11 22:41:34 +00:00
John Criswell
01d45827a1
Added LLVM copyright header.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9305 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-20 20:20:30 +00:00
Alkis Evlogimenos
73ff5120eb
Change MRegisterDesc::AliasSet, TargetInstrDescriptor::ImplicitDefs
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and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check for
pointer validity when iterating over those sets. Code that looked
like:
if (const unsigned* AS = TID.ImplicitDefs) {
for (int i = 0; AS[i]; ++i) {
// use AS[i]
}
}
was changed to:
for (const unsigned* AS = TID.ImplicitDefs; *AS; ++AS) {
// use *AS
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8960 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-08 05:20:08 +00:00
Chris Lattner
7884b750c3
Start using the CodeGeneratorWrappers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7666 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-07 05:39:09 +00:00
Chris Lattner
bc01723605
Switch code over to being a TableGenBackend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7627 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-06 04:32:07 +00:00
Chris Lattner
a3ae6143c1
Finish the instruction info emitter
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7543 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 21:57:51 +00:00
Chris Lattner
33ccf7edff
Initial checkin of Instruction emitter, which just produces enum values so far
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7515 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 17:24:10 +00:00