Commit Graph

3495 Commits

Author SHA1 Message Date
Zoran Jovanovic
fadf07b882 [mips][mips64r6] Add SELEQZ and SELNEZ instructions
Differential Revision: http://reviews.llvm.org/D3743


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208987 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 13:40:57 +00:00
Zoran Jovanovic
b95580a711 [mips][mips64r6] Add Compact indexed jumps.
Differential Revision: http://reviews.llvm.org/D3707


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208981 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 13:19:46 +00:00
Zoran Jovanovic
2b3ef615ca [mips][mips64r6] Add Compact zero-compare branch-and-link instructions
Differential Revision: http://reviews.llvm.org/D3718


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208977 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 12:27:19 +00:00
Zoran Jovanovic
b8c3bcbbfa [mips][mips64r6] Add compact branch instructions
Differential Revision: http://reviews.llvm.org/D3691


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208974 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 11:03:45 +00:00
Zoran Jovanovic
e4dfc196e4 [mips][mips64r6] Add LWPC and LWUPC instructions
Differential Revision: http://reviews.llvm.org/D3788


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208971 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 10:27:10 +00:00
Zoran Jovanovic
5f32c76db1 [mips][mips64r6] Add Floating Point Compare setting Mask - CMP.condn.fmt
Differential Revision: http://reviews.llvm.org/D3750


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208970 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 09:48:29 +00:00
Tim Northover
a9a94ce839 TableGen: fix operand counting for aliases
TableGen has a fairly dubious heuristic to decide whether an alias should be
printed: does the alias have lest operands than the real instruction. This is
bad enough (particularly with no way to override it), but it should at least be
calculated consistently for both strings.

This patch implements that logic: first get the *correct* string for the
variant, in the same way as the Matcher, without guessing; then count the
number of whitespace chars.

There are basically 4 changes this brings about after the previous
commits; all of these appear to be good, so I have changed the tests:

+ ARM64: we print "neg X, Y" instead of "sub X, xzr, Y".
+ ARM64: we skip implicit "uxtx" and "uxtw" modifiers.
+ Sparc: we print "mov A, B" instead of "or %g0, A, B".
+ Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208969 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 09:42:04 +00:00
Zoran Jovanovic
fbe77b1c6a [mips][mips64r6] Add Floating Point Fused Multiply Add Subtract
Differential Revision: http://reviews.llvm.org/D3727


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208952 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 08:42:27 +00:00
Bradley Smith
fd76d8a72d [ARM64] Improve diagnostics for Cn operands in SYS instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208902 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 16:28:32 +00:00
Zoran Jovanovic
1f05322d96 [mips][mips64r6] Add CLASS.fmt instructions
Differential Revision: http://reviews.llvm.org/D3712


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208894 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 15:16:36 +00:00
Zoran Jovanovic
75999124df [mips][mips64r6] Add RINT.fmt instructions
Differential Revision: http://reviews.llvm.org/D3711


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208892 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 15:04:37 +00:00
Zoran Jovanovic
c8d4dfc48b [mips][mips64r6] Add SELEQZ/SELNEZ.fmt instructions
Differential Revision: http://reviews.llvm.org/D3710


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208891 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 14:58:42 +00:00
Zoran Jovanovic
bd80605e28 [mips][mips64r6] Add MAX/MIN/MAXA/MINA.fmt instructions
Differential Revision: http://reviews.llvm.org/D3709


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208890 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 14:54:06 +00:00
Daniel Sanders
9f6a386e6a [mips][mips64r6] Add bitswap, and dbitswap
Summary: Depends on D3728

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3729

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208877 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 12:18:23 +00:00
Tim Northover
0a088b1fc5 ARM64: print correct aliases for NEON mov & mvn instructions
In all cases, if a "mov" alias exists, it is the canonical form of the
instruction. Now that TableGen can support aliases containing syntax variants,
we can enable them and improve the quality of the asm output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208874 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 12:11:02 +00:00
Daniel Sanders
8b580ccba0 [mips][mips64r6] Add align and dalign
Summary: Depends on D3689

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3728

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208872 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 12:06:36 +00:00
Tim Northover
f61a467a59 TableGen/ARM64: print aliases even if they have syntax variants.
To get at least one use of the change (and some actual tests) in with its
commit, I've enabled the AArch64 & ARM64 NEON mov aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208867 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 11:16:32 +00:00
Bradley Smith
75aa5372bc [ARM64] Improve load/store diagnostics and forbid 32-bit register addresses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208864 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 11:08:30 +00:00
Bradley Smith
dbe4f8b96e [ARM64] Add/Fixup diagnostics for floating point immediates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208862 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 11:07:28 +00:00
Daniel Sanders
06961bf147 [mips][mips64r6] Add addiupc, aluipc, and auipc
Summary:
No support for symbols in place of the immediate yet since it requires new
relocations.

Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3689

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208858 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 10:45:58 +00:00
Daniel Sanders
fc4953bff2 [mips][mips64r6] Add aui, daui, dahi, and dati
Summary: Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3759

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208857 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 10:27:19 +00:00
Daniel Sanders
9cfa5cf7ae [mips][mips64r6] Test that branch likelies are not accepted on MIPS64r6.
Summary:
They aren't implemented for any ISA at the moment.

Depends on D3670

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208855 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 09:47:43 +00:00
Daniel Sanders
f6741d6bdd [mips] Test that IAS for -mcpu=mips5 does not accept MIPS64 insns and -mcpu=mips(5|64) does not accept MIPS64r2
Summary:
To limit the number of tests required, only one 64-bit ISA prior to MIPS64 are tested.

rdhwr has been deliberately left without an ISA annotation for now. This is
because the assembler and CodeGen disagree on when the instruction is
available. Strictly speaking, it is only available in MIPS32r2 and
MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is
necessary for TLS so CodeGen should emit it on older ISA's too.

Depends on D3697

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3698

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208785 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14 15:35:03 +00:00
Daniel Sanders
7214d26b7c [mips][mips64r6] Add sel.s and sel.d
Summary:
Also use named constants for common opcode fields.

Depends on D3669

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3670

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208784 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14 15:29:44 +00:00
Saleem Abdulrasool
0fe443d893 ARM: implement support for the UDF mnemonic
The UDF instruction is a reserved undefined instruction space.  The assembler
mnemonic was introduced with ARM ARM rev C.a.  The instruction is not predicated
and the immediate constant is ignored by the CPU.  Add support for the three
encodings for this instruction.

The changes to the invalid instruction test is due to the fact that the invalid
instructions actually overlap with the undefined instruction.  Introduction of
the new instruction results in a partial decode as an undefined sequence.  Drop
the tests as they are invalid instruction patterns anyways.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208751 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14 03:47:39 +00:00
Christian Pirker
ad5d56c168 ARM: Additional test files for thumb fixups (checked with llvm-mv -show-encoding)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208712 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 17:06:51 +00:00
Christian Pirker
3beea23c1b ARM: Additional test files for thumb fixups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208691 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 11:50:39 +00:00
Daniel Sanders
0e0f907356 [mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-3 that was available in MIPS32R2.

To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are tested.

rdhwr has been deliberately left without an ISA annotation for now. This is
because the assembler and CodeGen disagree on when the instruction is
available. Strictly speaking, it is only available in MIPS32r2 and
MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is
necessary for TLS so CodeGen should emit it on older ISA's too.

Depends on D3696

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3697

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208690 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 11:45:36 +00:00
Kevin Qin
2a74dfe388 [ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode.
A vague diagnostic replaced the misleading one.
This can fix bug 19502.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208669 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 07:35:12 +00:00
Adam Nemet
45fc47013f [Test] Trim unnecessary .c and .cpp from config.suffix in lit.local.cfg
Tested by comparing make check VERBOSE=1 before and after to make sure
no tests are missed.  (VERBOSE=1 prints the list of tests.)

Only one test :( remains where .cpp is required:

tools/llvm-cov/range_based_for.cpp:// RUN: llvm-cov range_based_for.cpp | FileCheck %s --check-prefix=STDOUT

The topic was discussed in this thread:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140428/214905.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 19:57:31 +00:00
Tim Northover
d6cd0381f6 TableGen: use PrintMethods to print more aliases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208607 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 18:04:06 +00:00
Matheus Almeida
db5b7e016a [mips] Move disassembler test (test_2r_msa64) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208594 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:59:34 +00:00
Matheus Almeida
4d28469a8d [mips] Move disassembler test (Mips MSA test_vec) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208592 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:31:45 +00:00
Matheus Almeida
d8527e2578 [mips] Move disassembler tests (Mips MSA test_i*, test_mi10) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208590 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:26:53 +00:00
Matheus Almeida
e9cd60685b [mips] Move disassembler tests (Mips MSA test_elm*) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208589 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:23:45 +00:00
Matheus Almeida
e18828fb2b [mips] Move disassembler tests (Mips MSA test_lsa, test_dlsa) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208588 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:20:46 +00:00
Matheus Almeida
f666827156 [mips] Move disassembler test (Mips MSA test_ctrlregs) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208587 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:16:59 +00:00
Matheus Almeida
86992065e6 [mips] Move disassembler test (Mips MSA test_bit) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208586 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:10:00 +00:00
Matheus Almeida
5e3662ae95 [mips] Move disassembler tests (Mips MSA test_2r, test_2rf, test_3r, test_3rf) into
correct folder.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208584 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:03:20 +00:00
Daniel Sanders
e44de6afea Revert: r208582 - [mips][mips64r6] Add sel.s and sel.d
Accidentally committed an unreviewed patch. Reverted it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208583 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 15:43:41 +00:00
Daniel Sanders
87010f33a8 [mips][mips64r6] Add sel.s and sel.d
Summary:
Also use named constants for common opcode fields.

Depends on D3669

Reviewers: jkolek, vmedic, zoran.jovanovic

Differential Revision: http://reviews.llvm.org/D3670

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208582 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 15:39:10 +00:00
Daniel Sanders
b1b144c65a [mips][mips64r6] Add d?div, d?mod, d?divu, d?modu
Summary: Depends on D3668

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3669

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208579 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 15:24:16 +00:00
Daniel Sanders
d76eeb1bce [mips][mips64r6] Added mul/mulu/muh/muhu
Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3668

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208576 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 15:12:45 +00:00
Daniel Sanders
b6569388b9 [mips] Marked up instructions added in MIPS32 and tested that IAS for -mcpu=mips2 does not accept them
Summary:
To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are explicitly tested.

Depends on D3695

Reviewers: vmedic

Differential Revision: http://reviews.llvm.org/D3696

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208549 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 13:04:32 +00:00
Daniel Sanders
31546cd352 [mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-V that was available in MIPS32R2

Most of these instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now. It happens
because many of the MIPS V instructions have not been implemented.

Depends on D3694

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208546 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 12:52:44 +00:00
Daniel Sanders
b396af3752 [mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64
Summary:
DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no
effect on the CodeGen tests since expansion of i64 prevented their use
anyway.

The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as
well. This is not a functional change since DCLZ is still prohibited by
being a MIPS64 instruction (MIPS16 is only compatible with MIPS32).

No functional change

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3694

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208544 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 12:41:59 +00:00
Daniel Sanders
d46b2e219d [mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2
Summary:
dsbh and dshd are not available on Mips32r2. No codegen test changes
required since expansion of i64 prevented the use of these instructions
anyway.

Depends on D3690

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3692

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208542 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 12:15:41 +00:00
Bradley Smith
b0b587163d [ARM64] Add proper bounds checking/diagnostics to logical shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208540 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 11:49:16 +00:00
Bradley Smith
0ce7616654 [ARM64] Correct more bounds checks/diagnostics for arithmetic shift operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208528 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 09:41:43 +00:00
Daniel Sanders
7ef85447c9 [mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=mips[123] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-IV that was available in MIPS32

A small number of instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now.

Depends on D3676

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3677

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208414 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 14:06:17 +00:00