Commit Graph

18667 Commits

Author SHA1 Message Date
Jim Grosbach
df8fe9901d ARM Asm parsing of Thumb2 move immediate.
Thumb2 MOV mnemonic can accept both cc_out and predication. We don't (yet)
encode the instruction properly, but this gets the parsing part.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133945 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 21:38:03 +00:00
Evan Cheng
15993f83a4 More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 21:26:13 +00:00
Jim Grosbach
d1f0bbee18 Add exception necessitated by 133938.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 20:59:10 +00:00
Jim Grosbach
660a9ec4aa ARM assembly carry set/clear condition code aliases for 'hi/lo'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133938 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 20:40:29 +00:00
Jim Grosbach
fbd01783a6 ARM assembler support for ldmfd/stmfd mnemonics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 20:32:18 +00:00
Jim Grosbach
0d06bb9548 ARM assembler support for vpush/vpop.
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.

rdar://9683231



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133932 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 20:00:07 +00:00
Jim Grosbach
0ff9220ccb ARM Assembly syntax support for arithmetic implied dest operand.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
  sub r2, r2, #6
  sub r2, #6

rdar://9682597



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 19:09:15 +00:00
Evan Cheng
73f50d9bc3 Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 18:32:37 +00:00
Jakob Stoklund Olesen
1baeb006d2 Grow the X86FloatingPoint register map to hold 16 registers.
This allows for more live scratch registers which is needed to handle
live ST registers before return and inline asm instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 04:08:36 +00:00
Chad Rosier
14d71aac84 Replace dyn_cast<> with cast<> since the cast is already guarded by the necessary check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 18:51:28 +00:00
Dan Bailey
84149460d5 PTX: Reverting implementation of i8.
The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is
not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support
boolean values.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 18:16:28 +00:00
Chad Rosier
df78fcd2d6 Enable tail call optimization in the presence of a byval (x86-32 and x86-64).
<rdar://problem/9483883>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133858 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 02:04:56 +00:00
Douglas Gregor
ba3dc10702 Unbreak CMake build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 00:51:50 +00:00
Evan Cheng
4219718180 Add include guard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 23:59:54 +00:00
Evan Cheng
46af0d7341 Rename TargetDesc to MCTargetDesc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133846 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 23:53:19 +00:00
Jim Grosbach
ba8297ec08 Refactor MachO relocation generaration into the Target directories.
Move the target-specific RecordRelocation logic out of the generic MC
MachObjectWriter and into the target-specific object writers. This allows
nuking quite a bit of target knowledge from the supposedly target-independent
bits in lib/MC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133844 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 23:44:37 +00:00
Rafael Espindola
1189027f9d Fix cmake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 22:01:28 +00:00
Chad Rosier
2416da36ac Hoist simple check above more complex checking to avoid unnecessary
overheads.  No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133824 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 21:15:36 +00:00
Evan Cheng
f5fa52ed06 - Add MCRegisterInfo registration machinery. Also added x86 registration routines.
- Rename TargetRegisterDesc to MCRegisterDesc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 20:42:09 +00:00
Jim Grosbach
8b45456700 ARM movw/movt fixups need to mask the high bits.
The fixup value comes in as the whole 32-bit value, so for the lo16 fixup,
the upper bits need to be masked off. Previously we assumed the masking had
already been done and asserted.

rdar://9635991

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133818 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 20:06:59 +00:00
Dan Bailey
b05a8a8f02 PTX: Add support for i8 type and introduce associated .b8 registers
The i8 type is required for boolean values, but can only use ld, st and mov instructions. The i1 type continues to be used for predicates.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 19:27:10 +00:00
Chad Rosier
ef01edf1e9 The Neon VCVT (between floating-point and fixed-point, Advanced SIMD)
instructions can be used to match combinations of multiply/divide and VCVT 
(between floating-point and integer, Advanced SIMD).  Basically the VCVT 
immediate operand that specifies the number of fraction bits corresponds to a 
floating-point multiply or divide by the corresponding power of 2.

For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a 
combination of VMUL and VCVT (floating-point to integer) as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vmul.f32        d16, d17, d16
  vcvt.s32.f32    d16, d16
becomes:
  vcvt.s32.f32    d16, d16, #3

Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a 
combinations of VCVT (integer to floating-point) and VDIV as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vcvt.f32.s32    d16, d16
  vdiv.f32        d16, d17, d16
becomes:
  vcvt.f32.s32    d16, d16, #3

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 19:23:04 +00:00
Justin Holewinski
4799729d67 PTX: Add preliminary support for outputting debug information in the form of
.file and .loc directives.

Ideally, we would utilize the existing support in AsmPrinter for this, but
I cannot find a way to get .file and .loc directives to print without the
rest of the associated DWARF sections, which ptxas cannot handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 19:19:18 +00:00
Akira Hatanaka
25eba399cb Change the chain input of nodes that load the address of a function. This change
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 19:01:25 +00:00
Akira Hatanaka
8b2b713f68 Prevent generation of redundant addiu instructions that compute address of
static variables or functions. 




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133803 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 17:55:19 +00:00
Justin Holewinski
35f4fb34ff PTX: Re-work target sm/compute selection and add some basic GPU
targets: g80, gt200, gf100(fermi)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133799 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 16:27:49 +00:00
Rafael Espindola
ce117be633 Fix CellSPU CMakeList.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133792 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 13:58:45 +00:00
Evan Cheng
6db5d55ec3 Fix CellSPU CMakeLists.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133787 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 05:04:48 +00:00
Evan Cheng
a347f85dbe Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 01:44:41 +00:00
Eli Friedman
a390a1aa48 Add support for movntil/movntiq mnemonics. Reported on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133759 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 21:07:47 +00:00
Evan Cheng
f05589d043 Rename TargetOptions::StackAlignment to StackAlignmentOverride.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 18:15:47 +00:00
Evan Cheng
df214fa517 Remove TargetOptions.h dependency from ARMSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133738 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 18:15:17 +00:00
Justin Holewinski
d8149c1bef PTX: Always use registers for return values, but use .param space for device
parameters if SM >= 2.0

- Update test cases to be more robust against register allocation changes
- Bump up the number of registers to 128 per type
- Include Python script to re-generate register file with any number of
  registers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 18:10:13 +00:00
Justin Holewinski
486ca24c08 PTX: Whitespace fixes and remove commented out code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133734 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 18:10:07 +00:00
Justin Holewinski
a5ccb4e974 PTX: Prevent DCE from eliminating st.param calls, and unify the handling of
st.param and ld.param

FIXME: Test cases still need to be updated

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133733 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 18:10:05 +00:00
Justin Holewinski
67a9184861 PTX: Use .param space for parameters in device functions for SM >= 2.0
FIXME: DCE is eliminating the final st.param.x calls, figure out why

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133732 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 18:10:03 +00:00
Evan Cheng
ef41ff618f Remove TargetOptions.h dependency from X86Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 17:54:54 +00:00
Dylan Noblesmith
4dd26ddf8e CppBackend: fixup for api change
This broke after r133364.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 12:11:37 +00:00
Jay Foad
95c3e48f95 Reinstate r133513 (reverted in r133700) with an additional fix for a
-Wshorten-64-to-32 warning in Instructions.h.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 09:09:15 +00:00
Eric Christopher
e59fbc04ad Revert r133513:
"Reinstate r133435 and r133449 (reverted in r133499) now that the clang
self-hosted build failure has been fixed (r133512)."

Due to some additional warnings.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133700 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 06:24:52 +00:00
Bill Wendling
4c0c446d74 Use the presence of the __compact_unwind section to indicate that a target
supports compact unwind info instead of having a separate flag indicating this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133685 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 05:13:28 +00:00
Evan Cheng
2fa82bc3da Get rid of one getStackAlignment(). RegisterInfo shouldn't need to know about stack alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133679 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 01:53:43 +00:00
Bill Wendling
1a3ab63cb5 Add a flag that indicates whether a target supports compact unwind info or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22 23:16:51 +00:00
Bill Wendling
aa0a8f3177 Add a __LD,__compact_unwind section.
If the linker supports it, this will hold the CIE and FDE information in a
compact format. The implementation of the compact unwinding emission is coming
soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133658 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22 22:22:24 +00:00
Jim Grosbach
d7d71a1859 Add missing header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133640 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22 20:40:30 +00:00
Jim Grosbach
2fc6898886 Move ARMMachObjectWriter to its own file.
Just tidy up a bit. No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133638 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22 20:14:52 +00:00
Justin Holewinski
08d03168f2 PTX: Fix FrameIndex mapping bug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133619 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22 16:07:03 +00:00
Dan Bailey
3e8cff47a7 Test Commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133613 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22 09:04:30 +00:00
Justin Holewinski
6332fdef15 PTX: Add signed integer comparisons
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133599 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22 02:09:50 +00:00
Justin Holewinski
a9c85f9ead PTX: Add .address_size directive if PTX version >= 2.3
Patch by Wei-Ren Chen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22 00:43:56 +00:00