Jakob Stoklund Olesen
f28987b76e
Use set operations instead of plain lists to enumerate register classes.
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This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.
I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 23:28:14 +00:00
Jakob Stoklund Olesen
2a9d1ca9c2
Remove custom allocation order boilerplate that is no longer needed.
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The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.
Some targets still use custom allocation orders:
ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.
X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.
SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 16:56:59 +00:00
Rafael Espindola
03dc1868d1
Fix to match the dwarf register numbers that gdb uses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 03:58:16 +00:00
Venkatraman Govindaraju
f661277a9b
Multiple SPARC backend fixes: added Y register; updated select_cc, subx, subxcc defs/uses;
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and fixed CustomInserter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122607 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-28 20:39:17 +00:00
Jakob Stoklund Olesen
ca561ffcf3
Replace the SubRegSet tablegen class with a less error-prone mechanism.
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A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:27:12 +00:00
Jakob Stoklund Olesen
b555609e73
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
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This reverts commit 104654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 01:21:14 +00:00
Jakob Stoklund Olesen
6a45d681e5
Replace the SubRegSet tablegen class with a less error-prone mechanism.
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A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:28:19 +00:00
Chris Lattner
db486a6d53
several major improvements to the sparc backend: support for weak linkage
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and PIC codegen. Patch by Venkatraman Govindaraju!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81877 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-15 17:46:24 +00:00
Chris Lattner
4ee451de36
Remove attribution from file headers, per discussion on llvmdev.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Anton Korobeynikov
f191c80cd7
Use TableGen to emit information for dwarf register numbers.
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This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-11 19:50:10 +00:00
Evan Cheng
03494d7c8f
Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39843 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-13 23:55:50 +00:00
Chris Lattner
5ea64fd9eb
Constify some methods. Patch provided by Anton Vayvod, thanks!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29756 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-17 22:00:08 +00:00
Jim Laskey
ff70fe61ed
D'oh - should be even numbered.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27088 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 22:48:02 +00:00
Jim Laskey
47622e3721
Add dwarf register numbering to register data.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 21:15:58 +00:00
Chris Lattner
f613fcb741
Update to new-style flags usage, simplifying the .td file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26106 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-10 06:58:25 +00:00
Chris Lattner
7c90f73a1b
Rename SPARC V8 target to be the LLVM SPARC target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25985 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-05 05:50:24 +00:00
Chris Lattner
85e42b45ac
Reserve G1 for frame offset stuff and use it to handle large stack frames.
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For example, instead of emitting this:
test:
save -40112, %o6, %o6 ;; imm too large
add %i6, -40016, %o0 ;; imm too large
call caller
nop
restore %g0, %g0, %g0
retl
nop
emit this:
test:
sethi 4194264, %g1
or %g1, 848, %g1
save %o6, %g1, %o6
sethi 4194264, %g1
add %g1, %i6, %g1
add %i1, 944, %o0
call caller
nop
restore %g0, %g0, %g0
retl
nop
which doesn't cause the assembler to barf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24880 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 07:56:31 +00:00
Chris Lattner
8ba0423660
Elimiante SP and FP, which weren't members of the IntRegs register class
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24844 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-19 00:06:52 +00:00
Chris Lattner
4d55aca87a
Add initial conditional branch support. This doesn't actually work yet due
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to a bug in the scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24807 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-18 01:20:35 +00:00
Chris Lattner
37949f5c2b
Add patterns for multiply, simplify Y register handling stuff, add RDY instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24796 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 22:22:53 +00:00
Nate Begeman
6510b22cec
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
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work. This change has no effect on generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 04:51:06 +00:00
Chris Lattner
ecbce617ca
Split RegisterClass 'Methods' into MethodProtos and MethodBodies
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22929 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 19:13:20 +00:00
Chris Lattner
28e728d75a
put reg classes in namespaces
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22922 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 18:49:22 +00:00
Brian Gaeke
8fe429d0c2
Make this file self-contained.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18736 91177308-0d34-0410-b5e6-96231b3b80d8
2004-12-10 04:46:30 +00:00
Brian Gaeke
4b92ed6d58
Allocate fewer registers and tighten up alignment restrictions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17929 91177308-0d34-0410-b5e6-96231b3b80d8
2004-11-18 00:25:20 +00:00
Misha Brukman
f90a656a9f
SparcV8 int regs are not only 32-bits in width, but they are 32-bit aligned!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16526 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-27 18:22:18 +00:00
Misha Brukman
c6e7430499
Fix the copy-pasto that Brian noticed: V8 int regs are 32-bits wide, not 64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16518 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-26 21:07:43 +00:00
Misha Brukman
c95759c2f5
Use the V8/V9 shared register file description
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16485 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-22 21:48:50 +00:00
Chris Lattner
1002013ed3
Changes to make this work with Jason's patch. I checked this by hand, but
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would appreciate if others would also look at this to make sure I didn't
botch something obvious
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16312 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-13 21:32:03 +00:00
Chris Lattner
0e362770d0
Convert bytes to bits in alignment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15971 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-21 20:09:46 +00:00
Brian Gaeke
60c73e4f23
Make the double-fp pseudo registers be "NamedRegs".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14366 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-24 09:23:21 +00:00
Brian Gaeke
be81e82afc
The long integer pseudo-regs are history. So long, we hardly knew ye.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14364 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-24 08:55:21 +00:00
Brian Gaeke
f54d912e32
Add pseudo-registers and register class for 64-bit integer values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14332 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-22 20:14:41 +00:00
Brian Gaeke
4f217fdd10
Mess around with allocation order. In particular, I think we ought to be
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using the local & in regs first because they are not clobbered by calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14228 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-18 08:19:08 +00:00
Chris Lattner
f97b31e9cf
Merge my changes with brians
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12736 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-07 04:05:49 +00:00
Brian Gaeke
59e04e4889
Add support for the "Y" register, used by MUL & DIV.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12734 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-07 04:01:11 +00:00
Chris Lattner
9b3c702614
Avoid allocating special registers a bit more robustly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12207 91177308-0d34-0410-b5e6-96231b3b80d8
2004-03-08 03:48:07 +00:00
Brian Gaeke
bda4a3c61a
Hack it so we do not try to allocate values to G0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12184 91177308-0d34-0410-b5e6-96231b3b80d8
2004-03-06 05:31:32 +00:00
Brian Gaeke
da69e7d9b3
Double-FP pseudo-registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12112 91177308-0d34-0410-b5e6-96231b3b80d8
2004-03-04 05:15:03 +00:00
Brian Gaeke
e7173b7e8e
Floating point regs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12110 91177308-0d34-0410-b5e6-96231b3b80d8
2004-03-04 04:37:22 +00:00
Chris Lattner
e1274de2c9
Implement initial prolog/epilog code insertion methods.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11979 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-29 05:18:30 +00:00
Chris Lattner
1c809c594b
Add an instruction selector capable of selecting 'ret void'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11973 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-29 00:27:00 +00:00
Chris Lattner
a85d46eea8
Tab completion is our friend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11957 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-28 19:45:39 +00:00