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4 Commits

Author SHA1 Message Date
Hao Liu
0f6ebf1aa3 [AArch64]Fix a problem that the register order of fmls/fmla by element is incorrect. 
E.g. the codegen result is 
     fmls v1.2s, v0.2s, v2.s[3]
which is expected to be
     fmls v0.2s, v1.2s, v2.s[3]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198001 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-25 07:12:34 +00:00
Jiangning Liu
eeabc572b9 Add missing pattern matches to support ACLE intrinsics of AArch64 NEON. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197993 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-25 01:22:51 +00:00
Jiangning Liu
35df2e8c7f Fix the AArch64 NEON bug exposed by checking constant integer argument range of ACLE intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195843 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-27 14:02:25 +00:00
Jiangning Liu
dd518bcc9d Implement aarch64 neon instruction set AdvSIMD (3V elem). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191944 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-04 09:20:44 +00:00