Commit Graph

60 Commits

Author SHA1 Message Date
Anton Korobeynikov
8f8e9f0830 It seems that OR operation does not affect status reg at all.
Remove impdef of SRW. This fixes PR4779


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83739 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-10 22:17:47 +00:00
Anton Korobeynikov
c6f729ed55 Allow symbols to start from the digit if target requests it. This allows, e.g. pinning
variables to specified absolute address. Make use of this feature for MSP430.
This unbreaks PR4776.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82227 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-18 16:57:42 +00:00
Dan Gohman
fce288fc91 Eliminate more uses of llvm-as and llvm-dis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 00:09:15 +00:00
Anton Korobeynikov
cd76128f18 Add dummy inline asm handling for 'r' constraint. This fixes PR4778
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80085 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-26 13:44:29 +00:00
Anton Korobeynikov
379a087cc7 Provide dynamic_stackalloc lowering for MSP430.
This fixes PR4769

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80001 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-25 17:00:23 +00:00
Dan Gohman
ae3a0be92e Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:49:04 +00:00
Eli Friedman
2ac8b324eb Fix for PR4235: to build a floating-point value from integer parts,
build an integer and cast that to a float.  This fixes a crash 
caused by trying to split an f32 into two f16's.

This changes the behavior in test/CodeGen/XCore/fneg.ll because that 
testcase now triggers a DAGCombine which converts the fneg into an integer
operation.  If someone is interested, it's probably possible to tweak 
the test to generate an actual fneg.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72162 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-20 06:02:09 +00:00
Anton Korobeynikov
e4fdb8b8ff Mark rotl/rotr as expand. This generates pretty ugly code, but this is better than nothing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71976 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-17 10:16:28 +00:00
Anton Korobeynikov
aceb620de8 Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71975 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-17 10:15:22 +00:00
Anton Korobeynikov
19f76f5263 Add MSP430 test for PR4136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71392 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-10 14:48:36 +00:00