We are bound to fail! For proper disassembly, the well-known encoding bits
of the instruction must be fully specified.
This also removes pseudo instructions from considerations of disassembly,
which is a better design and less fragile than the name matchings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100899 91177308-0d34-0410-b5e6-96231b3b80d8
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100892 91177308-0d34-0410-b5e6-96231b3b80d8
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Reviewed by Chris Latter and Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
