Commit Graph

119 Commits

Author SHA1 Message Date
Misha Brukman
3da94aec4d Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21428 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-22 00:00:37 +00:00
Chris Lattner
131ca38c60 Minor fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19761 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 20:59:38 +00:00
Chris Lattner
38c0751a12 This is the final big of factoring. This shares cases in suboperand
differences, which means that identical instructions (after stripping off
the first literal string) do not run any different code at all.  On the X86,
this turns this code:

    switch (MI->getOpcode()) {
    case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::AND32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::AND32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::OR32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::OR32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break;
    case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break;
    case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break;
    case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
    }

into this:

    switch (MI->getOpcode()) {
    case X86::ADC32mi:
    case X86::ADC32mr:
    case X86::ADD32mi:
    case X86::ADD32mr:
    case X86::AND32mi:
    case X86::AND32mr:
    case X86::CMP32mi:
    case X86::CMP32mr:
    case X86::MOV32mi:
    case X86::MOV32mr:
    case X86::OR32mi:
    case X86::OR32mr:
    case X86::SBB32mi:
    case X86::SBB32mr:
    case X86::SHLD32mrCL:
    case X86::SHRD32mrCL:
    case X86::SUB32mi:
    case X86::SUB32mr:
    case X86::TEST32mi:
    case X86::TEST32mr:
    case X86::XCHG32mr:
    case X86::XOR32mi:
    case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::ADC32mi8:
    case X86::ADD32mi8:
    case X86::AND32mi8:
    case X86::OR32mi8:
    case X86::ROL32mi:
    case X86::ROR32mi:
    case X86::SAR32mi:
    case X86::SBB32mi8:
    case X86::SHL32mi:
    case X86::SHR32mi:
    case X86::SUB32mi8:
    case X86::TEST8mi:
    case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
    }

After this, the generated asmwriters look pretty much as though they were
generated by hand.  This shrinks the X86 asmwriter.inc files from 55101->39669
and 55429->39551 bytes each, and PPC from 16766->12859 bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19760 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 20:31:17 +00:00
Chris Lattner
f876668518 Implement *even more* factoring. In particular, if all of the instruction
strings starts out with a constant string, we emit the string first, using
a table lookup (instead of a switch statement).

Because this is usually the opcode portion of the asm string, the differences
between the instructions have now been greatly reduced.  This allows many
more case statements to be grouped together.

This patch also allows instruction cases to be grouped together when the
instruction patterns are exactly identical (common after the opcode string
has been ripped off), and when the differing operand is a MachineInstr
operand that needs to be formatted.

The end result of this is a mean and lean generated AsmPrinter!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19759 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 19:22:23 +00:00
Jeff Cohen
615ed993e1 Fix VC++ compilation error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19757 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:50:10 +00:00
Chris Lattner
870c016934 Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:

  case PPC::ADD: O  << "add ";  printOperand(MI, 0, MVT::i64); O  << ", ";  prin
tOperand(MI, 1, MVT::i64); O  << ", ";  printOperand(MI, 2, MVT::i64); O  << '\n
'; break;
  case PPC::ADDC: O  << "addc ";  printOperand(MI, 0, MVT::i64); O  << ", ";  pr
intOperand(MI, 1, MVT::i64); O  << ", ";  printOperand(MI, 2, MVT::i64); O  << '
\n'; break;
  case PPC::ADDE: O  << "adde ";  printOperand(MI, 0, MVT::i64); O  << ", ";  pr
intOperand(MI, 1, MVT::i64); O  << ", ";  printOperand(MI, 2, MVT::i64); O  << '
\n'; break;
...

Emit code like this:

  case PPC::ADD:
  case PPC::ADDC:
  case PPC::ADDE:
  ...
    switch (MI->getOpcode()) {
    case PPC::ADD: O << "add "; break;
    case PPC::ADDC: O << "addc "; break;
    case PPC::ADDE: O << "adde "; break;
    ...
    }
    printOperand(MI, 0, MVT::i64);
    O << ", ";
    printOperand(MI, 1, MVT::i64);
    O << ", ";
    printOperand(MI, 2, MVT::i64);
    O << "\n";
    break;

This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too.  The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode.  Thus this fixes PR448.

-Chris


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19755 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:38:13 +00:00
Chris Lattner
f11ad9ef46 Fix the ::: problem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19754 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:18:59 +00:00
Chris Lattner
5765dba5ce Minor refactoring, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19753 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 17:40:38 +00:00
Chris Lattner
b0b55e74a0 Seperate asmstring parsing from emission. This allows the code to be simpler
and more understandable.  It also allows us to do simple things like fold
consequtive literal strings together.  For example, instead of emitting this
for the X86 backend:

  O  << "adc" << "l" << " ";

we now generate this:

  O << "adcl ";

*whoa* :)

This shrinks the X86 asmwriters from 62729->58267 and 65176->58644 bytes
for the intel/att asm writers respectively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19749 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 17:32:42 +00:00
Andrew Lenharth
2202bfa5a3 make double-dollar properly escape asmstrings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19740 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 00:35:22 +00:00
Chris Lattner
9d990a01a9 Don't emit the method into the llvm namespace, let the #includer decide where it goes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16934 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-12 16:21:18 +00:00
Chris Lattner
953c6fe112 Correctly parse variant notation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16637 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-03 20:19:02 +00:00
Chris Lattner
2c38413b3f Do not #include files into the llvm namespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15849 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-17 03:08:28 +00:00
Chris Lattner
175580c0f3 Make the AsmWriter a first-class tblgen object. Allow targets to specify
name of the generated asmwriter class, and the name of the format string.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15747 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-14 22:50:53 +00:00
Chris Lattner
9302ba416b Fix minor bug in previous checkin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15649 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-11 04:08:36 +00:00
Chris Lattner
1caef2c0a9 change how we invoke the printer. Instead of passing in the MO directly,
pass in the MI, operand number, and the type of the operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15645 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-11 02:23:23 +00:00
Chris Lattner
c3d5f3e12a Be picky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15400 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 08:55:34 +00:00
Chris Lattner
076efa771a Add support for asm printing machine instructions that have operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15391 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 07:43:02 +00:00
Chris Lattner
2e1f51b8a5 Initial cut at an asm writer emitter. So far, this only handles emission of
instructions, and only instructions that take no operands at that!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15386 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 05:59:33 +00:00