On the POWER7, adds and logical operations can also be handled
in the load/store pipelines. We'll call these IntSimple.
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This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.
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Loads and stores can have different pipeline behavior, especially on
embedded chips. This change allows those differences to be expressed.
Except for the 440 scheduler, there are no functionality changes.
On the 440, the latency adjustment is only by one cycle, and so this
probably does not affect much. Nevertheless, it will make a larger
difference in the future and this removes a FIXME from the 440 itin.
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FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
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Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
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