JF Bastien
e812ce5cbe
WebAssembly: add basic int/fp instruction codegen.
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Summary: This patch has the most basic instruction codegen for 32 and 64 bit int/fp.
Reviewers: sunfish
Subscribers: llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11193
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242201 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-14 21:13:29 +00:00
JF Bastien
7bfd515593
WebAssembly: basic instructions todo, and basic register info.
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Summary:
This code is based on AArch64 for modern backend good practice, and NVPTX for
virtual ISA concerns.
Reviewers: sunfish
Subscribers: aemerson, llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11070
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241923 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:23:10 +00:00
JF Bastien
b5ebaf3ae5
Unbreak WebAssembly build
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Summary: D11021 and D11045 didn't update the WebAssembly target's code. It's still experimental so all tests passed.
Reviewers: sunfish, joker.eph, echristo
Subscribers: llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241859 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:00:09 +00:00
Dan Gohman
8ef6f1e24b
[WebAssembly] Set the scheduling preference.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241637 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 22:38:06 +00:00
JF Bastien
610992baca
WebAssembly: add some TODO
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Reviewers: sunfish
Subscribers: llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D10971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241513 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 21:41:59 +00:00
Dan Gohman
44bc052f4d
[WebAssembly] Set the HasFloatingPointExceptions flag for WebAssembly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241302 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 21:36:25 +00:00
JF Bastien
1ff585db47
WebAssembly: start instructions
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Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.
Test Plan: ninja check
Reviewers: sunfish
Subscribers: jfb, llvm-commits
Differential Revision: http://reviews.llvm.org/D10880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241211 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 23:41:25 +00:00
Dan Gohman
1efcdba0e2
[WebAssembly] Define separate Target instances for 32-bit and 64-bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241193 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 21:42:34 +00:00
Dan Gohman
a74341308f
[WebAssembly] Initial WebAssembly backend
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This WebAssembly backend is just a skeleton at this time and is not yet
functional.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241022 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 23:51:55 +00:00
