Commit Graph

5 Commits

Author SHA1 Message Date
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 12:03:15 +00:00
Jakob Stoklund Olesen
fddb7667ca Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05 03:10:20 +00:00
Anton Korobeynikov
05011a8aba Provide instruction sizes & encoding. No opcodes yet (but not needed so far).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93553 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-15 21:18:39 +00:00
Anton Korobeynikov
3af4a0b4cb Add instruction formats & support stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93550 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-15 21:17:13 +00:00
Anton Korobeynikov
f2c3e179ec Dummy MSP430 backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70694 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-03 12:57:15 +00:00