Matt Arsenault
0c6d96cf16
R600: Implement isZExtFree.
...
This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204946 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 17:23:31 +00:00
Tom Stellard
d8c31046a9
R600/SI: Custom select 64-bit ADD
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 21:36:18 +00:00
Matt Arsenault
3560dd2dcd
R600/SI: Fix moveToVALU when the first operand is VSrc.
...
Moving into a VSrc doesn't always work, since it could be
replaced with an SGPR later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195042 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:55 +00:00
Matt Arsenault
9bc4b2c0da
R600/SI: Fix multiple SGPR reads when using VCC.
...
No other SGPR operands are allowed, so if VCC is
used, move the other to a VGPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:50 +00:00
Matt Arsenault
e64a289609
R600/SI: Implement add i64, but do not yet enable.
...
Test doesn't actually check the output. I need
to fix add i64 being matched for the addressing
calculations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:47 +00:00
