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12 Commits

Author SHA1 Message Date
Michael Liao
959ddbb5e0 Enhance bool simplifcation in X86 to handle more cases 
This patch is revised based on patch from Victor Umansky
<victor.umansky@intel.com>. More cases are handled in X86's bool
simplification, i.e.
- SETCC_CARRY
- value is truncated to i1 with AND

As a by-product, PR5443 is also fixed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179265 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-11 04:43:09 +00:00
Jakob Stoklund Olesen
ed18a3e6b2 Remove -join-physregs from the test suite. 
This option has been disabled for a while, and it is going away so I can
clean up the coalescer code.

The tests that required physreg joining to be enabled were almost all of
the form "tiny function with interference between arguments and return
value". Such functions are usually inlined in the real world.

The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly
rare.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157027 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-17 23:44:19 +00:00
Andrew Trick
922d314e8f Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 23:20:51 +00:00
Jakob Stoklund Olesen
49b2803ec2 Prepare remaining tests for -join-physreg going away. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130893 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 23:54:59 +00:00
Benjamin Kramer
c175a4bd7e X86: Fix the (saddo/ssub x, 1) -> incl/decl selection to check the right operand for 1. 
Found by inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-08 15:20:20 +00:00
NAKAMURA Takumi
52ae4cac4e Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126196 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:19:12 +00:00
Benjamin Kramer
f50125ecaa DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is illegal. The latter usually compiles into smaller code. 
example code:
unsigned foo(unsigned x, unsigned y) {
  if (x != 0) y--;
  return y;
}

before:
  _foo:                           ## @foo
    cmpl  $1, 4(%esp)             ## encoding: [0x83,0x7c,0x24,0x04,0x01]
    sbbl  %eax, %eax              ## encoding: [0x19,0xc0]
    notl  %eax                    ## encoding: [0xf7,0xd0]
    addl  8(%esp), %eax           ## encoding: [0x03,0x44,0x24,0x08]
    ret                           ## encoding: [0xc3]

after:
  _foo:                           ## @foo
    cmpl  $1, 4(%esp)             ## encoding: [0x83,0x7c,0x24,0x04,0x01]
    movl  8(%esp), %eax           ## encoding: [0x8b,0x44,0x24,0x08]
    adcl  $-1, %eax               ## encoding: [0x83,0xd0,0xff]
    ret                           ## encoding: [0xc3]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122455 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-22 23:17:45 +00:00
Chris Lattner
23a0199f05 now that addc/adde are gone, "ADDC" in the X86 backend uses EFLAGS results, 
the same as setcc.  Optimize ADDC(0,0,FLAGS) -> SET_CARRY(FLAGS).  This is
a step towards finishing off PR5443.  In the testcase in that bug we now  get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	sbbq	%rcx, %rcx
	testb	$1, %cl
	setne	%dl
	ret

instead of:

	movq	%rdi, %rax
	addq	%rsi, %rax
	movl	$0, %ecx
	adcq	$0, %rcx
	testq	%rcx, %rcx
	setne	%dl
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122219 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-20 01:37:09 +00:00
Chris Lattner
39ffcb7b62 We lower setb to sbb with the hope that the and will go away, when it 
doesn't, match it back to setb.

On a 64-bit version of the testcase before we'd get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	sbbb	%dl, %dl
	andb	$1, %dl
	ret

now we get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	setb	%dl
	ret




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122217 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-20 01:16:03 +00:00
Chris Lattner
b00cd1c899 merge a target-specific add test into x86 directory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95654 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-09 06:35:50 +00:00
Chris Lattner
7816239985 merge another test in, drop the trivially constant folded cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-09 06:33:27 +00:00
Chris Lattner
71d845c48a consolidate and filecheckize two tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95652 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-09 06:24:00 +00:00