6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-31 10:29:25 +00:00
Code Issues Projects Releases Wiki Activity
40,197 Commits 39 Branches 0 Tags 277 MiB
f00e74f4d6
Commit Graph

2 Commits

Author SHA1 Message Date
Evan Cheng
d880b97257 Handle a few more cases of folding load i64 into xmm and zero top bits. 
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50918 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-09 21:53:03 +00:00
Evan Cheng
7e2ff77ef0 Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-08 00:57:18 +00:00