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14652 Commits

Author SHA1 Message Date
Dan Gohman
effc8c5269 Set isTerminator on TRAP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103778 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 16:46:02 +00:00
Dan Gohman
c0c32ae5c2 Don't use isBarrier for the PowerPC sync instruction. isBarrier is for 
control barriers, not memory ordering barriers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103777 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 16:42:16 +00:00
Dan Gohman
7f357ec6d2 Add mayLoad and mayStore flags to instructions which missed them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103776 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 16:34:55 +00:00
Evan Cheng
22c687b642 Added a QQQQ register file to model 4-consecutive Q registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 02:13:41 +00:00
Evan Cheng
7f68719517 Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103749 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 00:21:45 +00:00
Evan Cheng
c4ca40eb5e Add comment about the pseudo registers QQ, each of which is a pair of Q registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103731 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 20:02:08 +00:00
Bob Wilson
1190c14b54 Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers. 
Do not use those for Thumb1 functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 19:58:24 +00:00
Oscar Fuentes
ed36aac081 CMake: fixes 64 bit Visual Studio IDE build. Fixes bug 4936. 
Patch by Dimitry Andric!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103727 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 19:34:06 +00:00
Anton Korobeynikov
61aeed11cd Properly set thread-local flag on globals during cpp emission 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103702 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 07:41:57 +00:00
Daniel Dunbar
1860e7dcfd Fix -Asserts warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103694 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 03:19:36 +00:00
Evan Cheng
69b9f9883e Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103692 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 01:12:06 +00:00
Evan Cheng
d929f77738 Expand VMOVQQ into a pair of VMOVQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103684 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 00:17:02 +00:00
Evan Cheng
020cc1b4d0 Mark some pattern-less instructions as neverHasSideEffects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 00:16:46 +00:00
Chris Lattner
b5505d0ee3 reapply r103668 with a fix. Never make "minor syntax changes" 
after testing before committing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103681 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 00:02:47 +00:00
Chris Lattner
3519f9d7d1 revert r103668 for now, it is apparently breaking things. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103677 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 23:40:59 +00:00
Chris Lattner
0de8e3f10a moffset forms of moves are x86-32 only, make the parser 
lower them to the correct x86-64 instructions since we 
don't have a clean way to handle this in td files yet.
rdar://7947184


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103668 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 23:13:36 +00:00
Evan Cheng
431300797b Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103667 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 23:13:12 +00:00
Chris Lattner
2745f6e920 fix the encoding of the obscure "moffset" forms of moves, i386 
part first.  rdar://7947184


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103660 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 22:48:24 +00:00
Evan Cheng
a4d73d01c4 Remove a dead fixme. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103642 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 20:20:22 +00:00
Rafael Espindola
18c1021ec1 Add support for movi32 of global values to the new (MC) asm printer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103576 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 05:16:34 +00:00
Evan Cheng
5bdc2aa264 vst instructions are modeled as this: 
v1024 = REG_SEQUENCE ...
v1025 = EXTRACT_SUBREG v1024, 5
v1026 = EXTRACR_SUBREG v1024, 6
      = VSTxx <addr>, v1025, v1026

The REG_SEQUENCE ensures the sources that feed into the VST instruction
are getting the right register allocation so they form a large super-
register. The extract_subreg will be coalesced away all would just work:
v1024 = REG_SEQUENCE ...
      = VSTxx <addr>, v1024:5, v1024:6

The problem is if the coalescer isn't run, the extract_subreg instructions
would stick around and there is no assurance v1025 and v1026 will get the
right registers.

As a short term workaround, teach the NEON pre-allocation pass to transfer
the sub-register indices over. An alternative would be do it 2addr pass
when reg_sequence's are eliminated. But that *seems* wrong and require
updating liveness information.

Another alternative is to do this in the scheduler when the instructions are
created. But that would mean somehow the scheduler this has to be done for
correctness reason. That's yucky as well. So for now, we are leaving this
in the target specific pass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103540 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 01:42:50 +00:00
Daniel Dunbar
0481449a05 MC/X86: Extend suffix matching hack to match 'q' suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103535 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 00:54:20 +00:00
Daniel Dunbar
a5f1d57f65 MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can 
be diced into atoms, and adjust getAtom() to take this into account.
 - This fixes relocations to symbols in fixed size literal sections, for
   example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103532 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 00:38:17 +00:00
Dan Gohman
a6cb641f48 Add initial kill flag support to FastISel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103529 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 23:54:07 +00:00
Evan Cheng
9647f3d981 Avoid breaking vstd when reg_sequence is not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 21:07:36 +00:00
Bill Wendling
f6d8481ada Simplify this logic of creating a default Features object. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103507 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 20:46:04 +00:00
Duncan Sands
16d8f8bd91 I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it 
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103495 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 20:16:09 +00:00
Dan Gohman
99dca4fde7 Remove the "WantsWholeFile" concept, as it's no longer needed. CBE 
and the others use the regular addPassesToEmitFile hook now, and
llc no longer needs a bunch of redundant code to handle the
whole-file case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103492 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 19:57:55 +00:00
Dan Gohman
ff7a562751 Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 17:31:57 +00:00
Dan Gohman
419e4f9263 Remove the TargetLowering::getSubtarget() virtual function, which 
was unused. TargetMachine::getSubtarget() is used instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 16:21:03 +00:00
Kalle Raiskila
2320a44b90 Make SPU backend not assert on jump tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103466 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 11:00:02 +00:00
Evan Cheng
fb3611daad Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 07:26:32 +00:00
Bill Wendling
3cbae239bb Don't create a StringRef with a NULL value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103455 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 01:33:39 +00:00
Evan Cheng
0ce537a9db Model some vst3 and vst4 with reg_sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103453 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 01:19:40 +00:00
Bill Wendling
81043ee5dc The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a 
string of features for that target. However LTO was using that string to pass
into the "create target machine" stuff. That stuff needed the feature string to
be in a particular form. In particular, it needed the CPU specified first and
then the attributes. If there isn't a CPU specified, it required it to be blank
-- e.g., ",+altivec". Yuck.

Modify the getDefaultSubtargetFeatures method to be a non-static member
function. For all attributes for a specific subtarget, it will add them in like
normal. It will also take a CPU string so that it can satisfy this horrible
syntax.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103451 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 00:30:02 +00:00
Evan Cheng
e9e2ba05de Model some vld3 instructions with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 21:26:24 +00:00
Evan Cheng
603afbfe2a Model vld2 / vst2 with reg_sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 17:34:18 +00:00
Kalle Raiskila
26c4cf4c6f Fix encoding of 'sf' and 'sfh' instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103399 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 08:13:49 +00:00
Nathan Jeffords
bb59732d18 updated handling dllexport in X86AsmPrinter 
changed dllexport code to use EmitBytes instead of EmitRawText, and changed the export option to use /EXPORT: instead of -export: on the windows platform

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-09 08:40:06 +00:00
Nathan Jeffords
071de920a0 made COFF target dllexport logic apply to all subtargets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-09 05:52:28 +00:00
Chris Lattner
b54b9ddaaf break coff symbol definition stuff out into proper MCStreamer callbacks, 
patch by Nathan Jeffords!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103346 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-08 19:54:22 +00:00
Jim Grosbach
4b77f6a85a Clean up the conditional for handling of sign_extend_inreg based on 
whether the extract instructions are available.

rdar://7956878



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 18:34:55 +00:00
Devang Patel
ed66bf5125 Use overloaded operators instead of DIDescriptor::getNode() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103276 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 18:19:32 +00:00
Kalle Raiskila
021b5ef903 Testing svn access with a note added to documentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103271 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 18:06:28 +00:00
Chris Lattner
eb40a0fd98 switch MCSectionCOFF from a syntactic to semantic representation, 
patch by Peter Housel!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103267 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 17:17:41 +00:00
Evan Cheng
435d499177 Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 02:04:02 +00:00
Evan Cheng
07a6d9391c Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 01:54:08 +00:00
Dan Gohman
0d881042c0 When rematerializing, use the debug location of the original 
instruction, rather than a location near where the new instruction
is being inserted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103232 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 01:28:10 +00:00
Evan Cheng
c10b5afbe8 Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 00:24:52 +00:00
Daniel Dunbar
c26ae5ab7e MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand. 
- This fixes "leal 0, %eax", for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103205 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 22:39:14 +00:00