Chris Lattner
b228657acc
Revamp the Register class, and allow the use of the RegisterGroup class to
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specify aliases directly in register definitions.
Patch contributed by Jason Eckhardt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16330 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-14 04:17:02 +00:00
Misha Brukman
8283ec7c1c
Register classes are target-dependent
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15861 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-17 05:10:31 +00:00
Nate Begeman
1cffdf0798
Fix frame pointer handling:
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Reserve R0 in store/load from stack slot for building >32k offsets from SP
or FP. This also requires we use R11 rather than R0 for holding the LR
value we want to save or restore. Also, tell the register allocator not
to use R31 (our FP) in functions that have a frame pointer. These changes
fix Burg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15807 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-16 01:52:12 +00:00
Chris Lattner
d15575d39f
Reenable the CCRC
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15752 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-15 05:31:15 +00:00
Misha Brukman
ef9468cfe5
Mark R2 as available for allocation on Darwin/PPC32, but not AIX/PPC64
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15673 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-12 00:10:01 +00:00
Misha Brukman
dceb457607
* Set the is64bit boolean flag in PowerPCRegisterInfo
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* Doubles are 8 bytes in 64-bit PowerPC, and use the general register class
* Use double-word loads and stores for restoring from/saving to stack
* Do not allocate R2 if compiling for AIX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15670 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-11 23:44:55 +00:00
Misha Brukman
5b5708106e
Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15631 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-10 22:47:03 +00:00
Misha Brukman
8c02c1cbb8
Renamed files:
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* PowerPCReg.td => PowerPCRegisterinfo.td
* PowerPCInstrs.td => PowerPCInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15295 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-27 23:29:16 +00:00
Misha Brukman
e862f306fb
LR is a 32-bit int reg
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15273 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-27 17:15:32 +00:00
Misha Brukman
86fd274790
* Enable allocation of registers r2-r10
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* Allocate registers 13-31 backwards (to be able to store them all at once)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14896 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-16 20:35:20 +00:00
Misha Brukman
15eb0a15e5
* Do not allocate r0 as we use it indiscriminantly in the instr selector.
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* Do not define CR register class because we don't (yet) have the i4 type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14551 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-01 21:24:50 +00:00
Misha Brukman
da7515a378
* Allow more registers to be allocated from the general register pool
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* Define the condition register class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14510 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-30 21:54:50 +00:00
Misha Brukman
8ee0100880
Only allocate non-volatile registers R13-31 (for now).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14500 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-29 23:35:32 +00:00
Misha Brukman
5dfe3a9c3b
Initial revision
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14283 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-21 16:55:25 +00:00