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62 Commits

Author SHA1 Message Date
Craig Topper
50bee42b54 Convert assert(0) to llvm_unreachable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149849 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 22:14:15 +00:00
Jim Grosbach
492be64772 Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143113 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 17:44:01 +00:00
Benjamin Kramer
59a4f9af0a Fix a silly off by one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135842 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-23 03:04:46 +00:00
Benjamin Kramer
71883edee2 Add more constness. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135838 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-23 01:40:15 +00:00
Benjamin Kramer
9df8567548 Turn the DenseSet in MCRegisterClass into a tblgenerated bit field. This should be faster and smaller. 
Goodbye static ctors and dtors!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135836 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-23 00:47:49 +00:00
Benjamin Kramer
8ca9a86203 Teach tblgen to emit MCRegisterClasses. 
- This currently introduces more instances of the static DenseSet dtor, but that should be fixable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135735 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 00:44:39 +00:00
Benjamin Kramer
a50c175fe3 Sink parts of TargetRegisterClass into MCRegisterClass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135683 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 17:26:50 +00:00
Evan Cheng
0e6a052331 Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down 
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 20:57:22 +00:00
Evan Cheng
e837dead3c - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-28 19:10:37 +00:00
Evan Cheng
5e6b4605bd Rename TargetRegisterDesc to MCRegisterDesc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133845 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-24 23:44:48 +00:00
Evan Cheng
f5fa52ed06 - Add MCRegisterInfo registration machinery. Also added x86 registration routines. 
- Rename TargetRegisterDesc to MCRegisterDesc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133820 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-24 20:42:09 +00:00
Evan Cheng
a347f85dbe Starting to refactor Target to separate out code that's needed to fully describe 
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-24 01:44:41 +00:00