Commit Graph

24396 Commits

Author SHA1 Message Date
Rafael Espindola
e04c0e3f8d Revert "InstCombine: Improvement to check if signed addition overflows."
This reverts commit r209746.

It looks it is causing a crash while building libcxx. I am trying to get a
reduced testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209762 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-28 18:48:10 +00:00
Rafael Espindola
665d42accf [pr19844] Add thread local mode to aliases.
This matches gcc's behavior. It also seems natural given that aliases
contain other properties that govern how it is accessed (linkage,
visibility, dll storage).

Clang still has to be updated to expose this feature to C.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209759 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-28 18:15:43 +00:00
Louis Gerbarg
a5423f2598 Add support for combining GEPs across PHI nodes
Currently LLVM will generally merge GEPs. This allows backends to use more
complex addressing modes. In some cases this is not happening because there
is PHI inbetween the two GEPs:

  GEP1--\
        |-->PHI1-->GEP3
  GEP2--/

This patch checks to see if GEP1 and GEP2 are similiar enough that they can be
cloned (GEP12) in GEP3's BB, allowing GEP->GEP merging (GEP123):

  GEP1--\                     --\                           --\
        |-->PHI1-->GEP3  ==>    |-->PHI2->GEP12->GEP3 == >    |-->PHI2->GEP123
  GEP2--/                     --/                           --/

This also breaks certain use chains that are preventing GEP->GEP merges that the
the existing instcombine would merge otherwise.

Tests included.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209755 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-28 17:38:31 +00:00
Hal Finkel
9b77161927 Revert "[DAGCombiner] Split up an indexed load if only the base pointer value is live"
This reverts r208640 (I've just XFAILed the test) because it broke ppc64/Linux
self-hosting. Because nearly every regression test triggers a segfault, I hope
this will be easy to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209747 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-28 15:33:19 +00:00
Rafael Espindola
e8075c6877 InstCombine: Improvement to check if signed addition overflows.
This patch implements two things:

1. If we know one number is positive and another is negative, we return true as
   signed addition of two opposite signed numbers will never overflow.

2. Implemented TODO : If one of the operands only has one non-zero bit, and if
   the other operand has a known-zero bit in a more significant place than it
   (not including the sign bit) the ripple may go up to and fill the zero, but
   won't change the sign. e.x -  (x & ~4) + 1

We make sure that we are ignoring 0 at MSB.

Patch by Suyog Sarda.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209746 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-28 15:30:40 +00:00
Hal Finkel
b8af23fe1e Revert "[PPC] Use alias symbols in address computation."
This reverts commit r209638 because it broke self-hosting on ppc64/Linux. (the
Clang-compiled TableGen would segfault because it jumped to an invalid address
from within _ZNK4llvm17ManagedStaticBase21RegisterManagedStaticEPFPvvEPFvS1_E
(which is within the command-line parameter registration process)).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209745 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-28 15:25:06 +00:00
Evgeniy Stepanov
0949668398 [asancov] Don't emit extra runtime calls when compiling without coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209721 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-28 09:26:46 +00:00
Tilmann Scheller
d8ba67b97b [AArch64] Add store post-index update folding regression tests for the load/store optimizer.
Add regression tests for the following transformation:

  str X, [x20]
   ...
  add x20, x20, #32
   ->
  str X, [x20], #32

with X being either w0, x0, s0, d0 or q0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209715 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-28 06:43:00 +00:00
Tilmann Scheller
4cbbe0d97e [AArch64] Add load post-index update folding regression tests for the load/store optimizer.
Add regression tests for the following transformation:

 ldr X, [x20]
  ...
 add x20, x20, #32
  ->
 ldr X, [x20], #32

 with X being either w0, x0, s0, d0 or q0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209711 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-28 05:44:14 +00:00
Sebastian Pop
421b2c571c remove constant terms
The delinearization is needed only to remove the non linearity induced by
expressions involving multiplications of parameters and induction variables.
There is no problem in dealing with constant times parameters, or constant times
an induction variable.

For this reason, the current patch discards all constant terms and multipliers
before running the delinearization algorithm on the terms. The only thing
remaining in the term expressions are parameters and multiply expressions of
parameters: these simplified term expressions are passed to the array shape
recognizer that will not recognize constant dimensions anymore: these will be
recognized as different strides in parametric subscripts.

The only important special case of a constant dimension is the size of elements.
Instead of relying on the delinearization to infer the size of an element,
compute the element size from the base address type. This is a much more precise
way of computing the element size than before, as we would have mixed together
the size of an element with the strides of the innermost dimension.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209691 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 22:41:45 +00:00
Arnaud A. de Grandmaison
08f32401a9 No need for those tests to go thru llvm-as and/or llvm-dis.
opt can handle them by itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209689 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 22:03:28 +00:00
Sasa Stankovic
95ce098219 [mips] Optimize long branch for MIPS64 by removing %higher and %highest.
%higher and %highest can have non-zero values only for offsets greater
than 2GB, which is highly unlikely, if not impossible when compiling a
single function. This makes long branch for MIPS64 3 instructions smaller.

Differential Revision: http://llvm-reviews.chandlerc.com/D3281.diff


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209678 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 18:53:06 +00:00
David Blaikie
41087d99df DebugInfo: Create abstract function definitions even when concrete definitions preceed inline definitions.
After much puppetry, here's the major piece of the work to ensure that
even when a concrete definition preceeds all inline definitions, an
abstract definition is still created and referenced from both concrete
and inline definitions.

Variables are still broken in this case (see comment in
dbg-value-inlined-parameter.ll test case) and will be addressed in
follow up work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209677 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 18:37:55 +00:00
David Blaikie
254d093f99 DebugInfo: Lazily construct subprogram definition DIEs.
A further step to correctly emitting concrete out of line definitions
preceeding inlined instances of the same program.

To do this, emission of subprograms must be delayed until required since
we don't know which (abstract only (if there's no out of line
definition), concrete only (if there are no inlined instances), or both)
DIEs are required at the start of the module.

To reduce the test churn in the following commit that actually fixes the
bug, this commit introduces the lazy DIE construction and cleans up test
cases that are impacted by the changes in the resulting DIE ordering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209675 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 18:37:48 +00:00
David Blaikie
def5a05797 DebugInfo: Lazily attach definition attributes to definitions.
This is a precursor to fixing inlined debug info where the concrete,
out-of-line definition may preceed any inlined usage. To cope with this,
the attributes that may appear on the concrete definition or the
abstract definition are delayed until the end of the module. Then, if an
abstract definition was created, it is referenced (and no other
attributes are added to the out-of-line definition), otherwise the
attributes are added directly to the out-of-line definition.

In a couple of cases this causes not just reordering of attributes, but
reordering of types. When the creation of the attribute is delayed, if
that creation would create a type (such as for a DW_AT_type attribute)
then other top level DIEs may've been constructed during the delay,
causing the referenced type to be created and added after those
intervening DIEs. In the extreme case, in cross-cu-inlining.ll, this
actually causes the DW_TAG_basic_type for "int" to move from one CU to
another.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209674 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 18:37:43 +00:00
Jingyue Wu
3efc250128 Fixed a test in r209670
The test was outdated with r209537.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209671 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 18:12:55 +00:00
Jingyue Wu
585644611e Distribute sext/zext to the operands of and/or/xor
This is an enhancement to SeparateConstOffsetFromGEP. With this patch, we can
extract a constant offset from "s/zext and/or/xor A, B".

Added a new test @ext_or to verify this enhancement.

Refactoring the code, I also extracted some common logic to function
Distributable. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209670 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 18:00:00 +00:00
David Blaikie
991c9c1c89 DebugInfo: Fix argument ordering in test by adding argument numbering.
This old test didn't have the argument numbering that's now squirelled
away in the high bits of the line number in the DW_TAG_arg_variable
metadata.

Add the numbering and update the test to ensure arguments are in-order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209669 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 17:57:14 +00:00
Filipe Cabecinhas
078862e67f Post-commit fixes for r209643
Detected by Daniel Jasper, Ilia Filippov, and Andrea Di Biagio
Fixed the argument order to select (the mask semantics to blendv* are the
inverse of select) and fixed the tests
Added parenthesis to the assert condition
Ran clang-format

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209667 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 16:54:33 +00:00
Tim Northover
fb26356bed AArch64: add test for NZCV cross-copy save.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209665 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 16:50:09 +00:00
Tim Northover
be5c8baeb6 AArch64: add AArch64-specific test for 'c' and 'n'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209664 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 16:50:03 +00:00
Bill Schmidt
3f01f5296e [PATCH] Correct type used for VADD_SPLAT optimization on PowerPC
In PPCISelLowering.cpp: PPCTargetLowering::LowerBUILD_VECTOR(), there
is an optimization for certain patterns to generate one or two vector
splats followed by a vector add or subtract.  This operation is
represented by a VADD_SPLAT in the selection DAG.  Prior to this
patch, it was possible for the VADD_SPLAT to be assigned the wrong
data type, causing incorrect code generation.  This patch corrects the
problem.

Specifically, the code previously assigned the value type of the
BUILD_VECTOR node to the newly generated VADD_SPLAT node.  This is
correct much of the time, but not always.  The problem is that the
call to isConstantSplat() may return a SplatBitSize that is not the
same as the number of bits in the original element vector type.  The
correct type to assign is a vector type with the same element bit size
as SplatBitSize.

The included test case shows an example of this, where the
BUILD_VECTOR node has a type of v16i8.  The vector to be built is {0,
16, 0, 16, 0, 16, 0, 16, 0, 16, 0, 16, 0, 16, 0, 16}.  isConstantSplat
detects that we can generate a splat of 16 for type v8i16, which is
the type we must assign to the VADD_SPLAT node.  If we do not, we
generate a vspltisb of 8 and a vaddubm, which generates the incorrect
result {16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
16}.  The correct code generation is a vspltish of 8 and a vadduhm.

This patch also corrected code generation for
CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll, which had been marked
as an XFAIL, so we can remove the XFAIL from the test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209662 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 15:57:51 +00:00
Zoran Jovanovic
61e341e0bf [mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16
Differential Revision: http://reviews.llvm.org/D3860


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209659 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 14:58:51 +00:00
Amara Emerson
87d192bb72 [ARM] Emit correct build attributes for the relocation models.
Patch by Asiri Rathnayake.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209656 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 13:30:21 +00:00
Zoran Jovanovic
f7744906f0 [mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2
Differential Revision: http://reviews.llvm.org/D3824


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209655 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 12:55:40 +00:00
Evgeniy Stepanov
18b6fb9612 [asancov] Emit an initializer passing number of coverage code locations in each module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209654 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 12:39:31 +00:00
Tim Northover
e43c5023fe ARM: teach AAPCS-VFP to deal with Cortex-M4.
Cortex-M4 only has single-precision floating point support, so any LLVM
"double" type will have been split into 2 i32s by now. Fortunately, the
consecutive-register framework turns out to be precisely what's needed to
reconstruct the double and follow AAPCS-VFP correctly!

rdar://problem/17012966

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209650 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 10:43:38 +00:00
Dinesh Dwivedi
f31b009b3e Adding testcase for PR18886.
Differential Revision: http://reviews.llvm.org/D3837



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209645 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 06:44:25 +00:00
Filipe Cabecinhas
c5f611404c Convert some X86 blendv* intrinsics into IR.
Summary:
Implemented an InstCombine transformation that takes a blendv* intrinsic
call and translates it into an IR select, if the mask is constant.

This will eventually get lowered into blends with immediates if possible,
or pblendvb (with an option to further optimize if we can transform the
pblendvb into a blend+immediate instruction, depending on the selector).
It will also enable optimizations by the IR passes, which give up on
sight of the intrinsic.

Both the transformation and the lowering of its result to asm got shiny
new tests.

The transformation is a bit convoluted because of blendvp[sd]'s
definition:

Its mask is a floating point value! This forces us to convert it and get
the highest bit. I suppose this happened because the mask has type
__m128 in Intel's intrinsic and v4sf (for blendps) in gcc's builtin.

I will send an email to llvm-dev to discuss if we want to change this or
not.

Reviewers: grosbach, delena, nadav

Differential Revision: http://reviews.llvm.org/D3859

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209643 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 03:42:20 +00:00
Rafael Espindola
f2928b9b5f [PPC] Use alias symbols in address computation.
This seems to match what gcc does for ppc and what every other llvm
backend does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209638 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 19:08:19 +00:00
Tim Northover
e0c2787cb7 AArch64: force i1 to be zero-extended at an ABI boundary.
This commit is debatable. There are two possible approaches, neither
of which is really satisfactory:

1. Use "@foo(i1 zeroext)" to mean an extension to 32-bits on Darwin,
   and 8 bits otherwise.
2. Redefine "@foo(i1)" to mean that the i1 is extended by the caller
   to 8 bits. This goes against the spirit of "zeroext" I think, but
   it's a bit of a vague construct anyway (by definition you're going
   to extend to the amount required by the ABI, that's why it's the
   ABI!).

This implements option 2. The DAG machinery really isn't setup for the
first (there's a fairly strong assumption that "zeroext" goes to at
least the smallest register size), and even if it was the resulting
DAG looks like it would be inferior in many cases.

Theoretically we could add AssertZext nodes in the consumers of
ABI-passed values too now, but this actually seems to make the code
worse in practice by making truncation proceed in two steps. The code
produced is equally valid if we continue to assume only the low bit is
defined.

Should fix PR19850

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209637 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 17:22:07 +00:00
Tim Northover
4146695fb2 AArch64: simplify calling conventions slightly.
We can eliminate the custom C++ code in favour of some TableGen to
check the same things. Functionality should be identical, except for a
buffer overrun that was present in the C++ code and meant webkit
failed if any small argument needed to be passed on the stack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 17:21:53 +00:00
Tilmann Scheller
7aac65de51 [AArch64] Add store + add folding regression tests for the load/store optimization pass.
Add tests for the following transform:

 str X, [x0, #32]
  ...
 add x0, x0, #32
  ->
 str X, [x0, #32]!

with X being either w1, x1, s0, d0 or q0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209627 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 13:36:47 +00:00
Tilmann Scheller
3390e6c4a8 [AArch64] Add more regression tests for the load/store optimization pass.
Cover the following cases:

  ldr X, [x0, #32]
   ...
  add x0, x0, #32
   ->
  ldr X, [x0, #32]!

with X being either w1, x1, s0, d0 or q0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209624 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 12:15:51 +00:00
Tilmann Scheller
852c0cc64f Remove accidentally committed whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209619 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 09:40:40 +00:00
Tilmann Scheller
47e3b43768 [AArch64] Add a regression test for the load store optimizer.
We have a couple of regression tests for load/store pairing, but (to my knowledge) there are no regression tests for the load/store + add/sub folding.

As a first step towards increased test coverage of this area, this commit adds a test for one instance of a load + add to pre-indexed load transformation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209618 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 09:37:19 +00:00
David Blaikie
bcc96923e0 DebugInfo: Test linkonce-odr functions under LTO.
This was previously regressed/broken by r192749 (reverted due to this
issue in r192938) and I was about to break it again by accident with
some more invasive changes that deal with the subprogram lists. So to
avoid that and further issues - here's a test.

It's a pretty basic test - in both r192749 and my impending case, this
test would crash, but checking the basics (that we put a subprogram in
just one of the two CUs) seems like a good start.

We still get this wrong in weird ways if the linkonce-odr function
happens to not be identical in the metadata (because it's defined in two
different files (hence the # line directives in this test), etc) even
though it meets the language requirements (identical token stream) for
such a thing. That results in two subprogram DIEs, but only one of them
gets the parameter and high/low pc information, etc. We probably need to
use the DIRef infrastructure to deduplicate functions as we do types to
address this issue - or perhaps teach the BC linker to remove the
duplicate entries in subprogram lists?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209614 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 06:44:52 +00:00
Rafael Espindola
524b8836c2 Just check the entire string.
Thanks to David Blaikie for the suggestion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209610 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 04:08:51 +00:00
David Blaikie
cec37248b2 DebugInfo: Fix inlining with #file directives a little harder
Seems my previous fix was insufficient - we were still not adding the
inlined function to the abstract scope list. Which meant it wasn't
flagged as inline, didn't have nested lexical scopes in the abstract
definition, and didn't have abstract variables - so the inlined variable
didn't reference an abstract variable, instead being described
completely inline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209602 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 18:11:35 +00:00
David Blaikie
7e79a350b5 Streamline test case by avoiding a temporary file and piping llc output straight to llvm-dwarfdump
We still do temporary files in many cases, just updating this particular
one because I was debugging it and made this change while doing so.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209601 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 15:38:52 +00:00
Rafael Espindola
c385367909 Emit data or code export directives based on the type.
Currently we look at the Aliasee to decide what type of export
directive to use. It seems better to use the type of the alias
directly. This is similar to how we handle the alias having the
same address but other attributes (linkage, visibility) from the
aliasee.

With this patch it is now possible to do things like

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-windows-msvc"
@foo = global [6 x i8] c"\B8*\00\00\00\C3", section ".text", align 16
@f = dllexport alias i32 (), [6 x i8]* @foo
!llvm.module.flags = !{!0}
!0 = metadata !{i32 6, metadata !"Linker Options", metadata !1}
!1 = metadata !{metadata !2, metadata !3}
!2 = metadata !{metadata !"/DEFAULTLIB:libcmt.lib"}
!3 = metadata !{metadata !"/DEFAULTLIB:oldnames.lib"}

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209600 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 12:49:07 +00:00
Rafael Espindola
fba226fc52 Make these CHECKs a bit more strict.
The " at the end of the line makes sure we matched the entire directive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209599 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 12:43:13 +00:00
Benjamin Kramer
9d934aca34 CodeGen: Make MachineBasicBlock::back skip to the beginning of the last bundle.
This makes front/back symmetric with begin/end, avoiding some confusion.
Added instr_front/instr_back for the old behavior, corresponding to
instr_begin/instr_end. Audited all three in-tree users of back(), all
of them look like they don't want to look inside bundles.

Fixes an assertion (PR19815) when generating debug info on mips, where a
delay slot was bundled at the end of a branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209580 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 13:13:17 +00:00
Tim Northover
29f94c7201 AArch64/ARM64: move ARM64 into AArch64's place
This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.

"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.

This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 12:50:23 +00:00
Tim Northover
9105f66d6f AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.
I'm doing this in two phases for a better "git blame" record. This
commit removes the previous AArch64 backend and redirects all
functionality to ARM64. It also deduplicates test-lines and removes
orphaned AArch64 tests.

The next step will be "git mv ARM64 AArch64" and rewire most of the
tests.

Hopefully LLVM is still functional, though it would be even better if
no-one ever had to care because the rename happens straight
afterwards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209576 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 12:42:26 +00:00
NAKAMURA Takumi
4ca8b0b66d llvm/test/Object/ar-error.test: Don't check the message "No such file or directory".
It didn't match on non-English version of Windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209570 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 08:47:11 +00:00
Michael Zolotukhin
45788be6e2 Implement sext(C1 + C2*X) --> sext(C1) + sext(C2*X) and
sext{C1,+,C2} --> sext(C1) + sext{0,+,C2} transformation in Scalar
Evolution.

That helps SLP-vectorizer to recognize consecutive loads/stores.

<rdar://problem/14860614>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209568 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 08:09:57 +00:00
Tim Northover
6a04ef99f6 ARM64: extract a 32-bit subreg when selecting an inreg extend
After the load/store refactoring, we were sometimes trying to feed a
GPR64 into a 32-bit register offset operand. This failed in
copyPhysReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209566 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 07:05:42 +00:00
David Blaikie
1288a3b8e6 DebugInfo: Generalize some tests to handle variations in attribute ordering.
In an effort to fix inlined debug info in situations where the out of
line definition of a function preceeds any inlined usage, the order in
which some attributes are added to subprogram DIEs may change. (in
essence, definition-necessary attributes like DW_AT_low_pc/high_pc will
be added immediately, but the names, types, and other features will be
delayed to module end where they may either be added to the subprogram
DIE or instead reference an abstract definition for those values)

These tests can be generalized to be resilient to this change. 5 or so
tests actually have to be incompatibly changed to cope with this
reordering and will go along with the change that affects the order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209554 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-23 21:11:46 +00:00
David Blaikie
3b39845adf DebugInfo: Generalize a test case to not depend on abbreviation numbering.
It's an unnecessary detail for this test and just gets in the way when
making unrelated changes to the output in this test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209553 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-23 21:07:01 +00:00