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Commit Graph

Author	SHA1	Message	Date
Nadav Rotem	f55ef64544	Generate better select code by allowing the target to use scalar select, and not sign-extend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163086 91177308-0d34-0410-b5e6-96231b3b80d8	2012-09-02 08:20:07 +00:00
Nadav Rotem	e757f00446	Currently targets that do not support selects with scalar conditions and vector operands - scalarize the code. ARM is such a target because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162926 91177308-0d34-0410-b5e6-96231b3b80d8	2012-08-30 19:17:29 +00:00

Author

SHA1

Message

Date

Nadav Rotem

f55ef64544

Generate better select code by allowing the target to use scalar select, and not sign-extend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163086 91177308-0d34-0410-b5e6-96231b3b80d8

2012-09-02 08:20:07 +00:00

Nadav Rotem

e757f00446

Currently targets that do not support selects with scalar conditions and vector operands - scalarize the code. ARM is such a target

because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR
to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2).

rdar://12201387



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162926 91177308-0d34-0410-b5e6-96231b3b80d8

2012-08-30 19:17:29 +00:00

2 Commits