4 Commits

Author	SHA1	Message	Date
Dan Gohman	ae3a0be92e	Split the Add, Sub, and Mul instruction opcodes into separate ... integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8	2009-06-04 22:49:04 +00:00
Chris Lattner	e12ecf272d	Implement basic support for the 'f' register class constraint. This basically ... works, but probably won't if you mix it with 't' or 'u' yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48243 91177308-0d34-0410-b5e6-96231b3b80d8	2008-03-11 19:50:13 +00:00
Chris Lattner	f30e1cf9b7	teach X86InstrInfo::copyRegToReg how to copy into ST(0) from ... an RFP register class. Teach ScheduleDAG how to handle CopyToReg with different src/dst reg classes. This allows us to compile trivial inline asms that expect stuff on the top of x87-fp stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48107 91177308-0d34-0410-b5e6-96231b3b80d8	2008-03-09 09:15:31 +00:00
Chris Lattner	02b6d25a27	Add ScheduleDAG support for copytoreg where the src/dst register are ... in different register classes, e.g. copy of ST(0) to RFP*. This gets some really trivial inline asm working that plops things on the top of stack (PR879) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48105 91177308-0d34-0410-b5e6-96231b3b80d8	2008-03-09 08:49:15 +00:00