don't visit all blocks in the function, and don't iterate over the split blocks'
predecessor lists for each block visited.
Also, remove the special-case test for the entry block. Splitting the entry
block isn't common enough to make this worthwhile.
This fixes a major compile-time bottleneck which is exposed now that
LoopSimplify isn't being redundantly run both before and after
DominanceFrontier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109408 91177308-0d34-0410-b5e6-96231b3b80d8
ReduceMiscompilingFunctions::TestFuncs. This makes the test functional
(i.e., no side effects).
Before we would end up using dead functions if a pass decided to remove them
(inline for example) and we would also keep broken functions and conclude that
that a single function was enough to reproduce the bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109387 91177308-0d34-0410-b5e6-96231b3b80d8
accept the flag and do nothing but warn about it, cleverly bypassing our
configure-based detection system. Patch by Takumi Nakamura!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109385 91177308-0d34-0410-b5e6-96231b3b80d8
hanging off a value, then the dropping code will intentionally not drop
it too (since this is almost certainly a bug).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109337 91177308-0d34-0410-b5e6-96231b3b80d8
instead of fixed size arrays, so that increasing FirstVirtualRegister to 16K
won't cause a compile time performance regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109330 91177308-0d34-0410-b5e6-96231b3b80d8
appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.
On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
function live in set. This will give us tGPR for Thumb1 and GPR otherwise,
so the copy will be spillable. rdar://8224931
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to be of a different register class. For example, in Thumb1 if the live-in is
a high register, we want the vreg to be a low register. rdar://8224931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109291 91177308-0d34-0410-b5e6-96231b3b80d8
comments explaining why it was wrong. 8225024.
Fix the real problem in 8213383: the code that splits very large
blocks when no other place to put constants can be found was not
considering the case that the block contained a Thumb tablejump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109282 91177308-0d34-0410-b5e6-96231b3b80d8
it's too late to start backing off aggressive latency scheduling when most
of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
For ARM, this is almost always a win on # of instructions. It's runtime
neutral for most of the tests. But for some kernels with high register
pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
54 and sped up by 20%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
