Commit Graph

21 Commits

Author SHA1 Message Date
Chris Lattner
ad3bc8d8ad Implement getConstraintType for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26042 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-07 20:16:30 +00:00
Chris Lattner
763317de1b Add the simple PPC integer constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26027 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-07 00:47:13 +00:00
Chris Lattner
ddc787dfdc add info about the inline asm register constraints for PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25853 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 19:20:21 +00:00
Chris Lattner
281b55ebec Use PPCISD::CALL instead of ISD::CALL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25717 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 23:34:02 +00:00
Chris Lattner
bba534dc66 Make llvm.frame/returnaddr not crash on ppc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25710 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 22:25:06 +00:00
Nate Begeman
ee625573b5 Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
the same functionality.  This addresses another piece of bug 680.  Next,
on to fixing Alpha VAARG, which I broke last time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25696 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 21:09:22 +00:00
Nate Begeman
acc398c195 First part of bug 680:
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25606 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-25 18:21:52 +00:00
Chris Lattner
da6d20f0c1 Give PPCISD:: nodes legible names in dumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25166 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-09 23:52:17 +00:00
Nate Begeman
9e4dd9dfc9 Pattern-match return. Includes gross hack!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24874 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 00:26:01 +00:00
Nate Begeman
993aeb2ed9 Prepare support for AltiVec multiply, divide, and sqrt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24700 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-13 22:55:22 +00:00
Chris Lattner
4172b10ca1 Use new PPC-specific nodes to represent shifts which require the 6-bit
amount handling that PPC provides.  These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits.  This fixes a miscompilation of crafty with
the new front-end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24615 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-06 02:10:38 +00:00
Chris Lattner
860e8862c1 Add an initial hack at legalizing GlobalAddress into the appropriate nodes
on Darwin to remove smarts from the isel.  This is currently disabled by
default (uncomment setOperationAction(ISD::GlobalAddress to enable it).
tblgen needs to become smarter about tglobaladdr nodes and bigger patterns
needed to be added to the .td file.  However, we can currently emit stuff like
this:  :)

        li r2, lo16(L_x$non_lazy_ptr)
        lis r3, ha16(L_x$non_lazy_ptr)
        lwzx r2, r3, r2

The obvious improvements will follow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24390 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-17 07:30:41 +00:00
Nate Begeman
4a95945fa5 Add the ability to lower return instructions to TargetLowering. This
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23802 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-18 23:23:37 +00:00
Nate Begeman
21e463b2bf More PPC32 -> PPC changes, as well as merging some classes that were
redundant after the change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-16 05:39:50 +00:00
Chris Lattner
2668959b88 Rename PowerPC*.h to PPC*.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-14 23:51:18 +00:00
Nate Begeman
c09eeec0eb Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when we
are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts,
such as the PowerPC 970.

This speeds up 189.lucas from 81.99 to 32.64 seconds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23250 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-06 22:03:27 +00:00
Chris Lattner
f76053269e Move FCTIWZ handling out of the instruction selectors and into legalization,
getting them out of the business of making stack slots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23180 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-31 21:09:52 +00:00
Chris Lattner
8a2d3ca7df implement SELECT_CC fully for the DAG->DAG isel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23101 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26 21:23:58 +00:00
Chris Lattner
0bbea95433 Make fsel emission work with both the pattern and dag-dag selectors, by
giving it a non-instruction opcode.  The dag->dag selector used to not
select the operands of the fsel, because it thought that whole tree was
already selected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23091 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26 20:25:03 +00:00
Chris Lattner
e4bc9ea0a5 add initial support for converting select_cc -> fsel in the legalizer
instead of in the backend.  This currently handles fsel cases with registers,
but doesn't have the 0.0 and -0.0 optimization enabled yet.

Once this is finished, special hack for fp immediates can go away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23075 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26 00:52:45 +00:00
Chris Lattner
7c5a3d390a Pull the LLVM -> DAG lowering code out of the pattern selector so that it
can be shared with the DAG->DAG selector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22799 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-16 17:14:42 +00:00