Vincent Lejeune
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dcfcf1d1ff
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R600: Factorize Fetch size limit inside AMDGPUSubTarget
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182122 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-05-17 16:49:55 +00:00 |
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Vincent Lejeune
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631591e6f3
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R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-04-30 00:13:39 +00:00 |
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Dmitri Gribenko
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96f498bd9f
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Remove redundant 'llvm::' qualifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172358 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-01-13 16:01:15 +00:00 |
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Tom Stellard
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f98f2ce29e
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Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-12-11 21:25:42 +00:00 |
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