Commit Graph

5 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
de67a51b66 Rename MachineVerifier pass to avoid command line collision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71987 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-17 19:37:14 +00:00
Jakob Stoklund Olesen
44b27e5c75 Verify that explicit definitions in the TargetInstrDesc are matched by
explicit register define operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71933 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-16 07:25:20 +00:00
Jakob Stoklund Olesen
d6fb97761e Allow redefinition of reserved registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71932 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-16 07:24:54 +00:00
Duncan Sands
e556720ea8 Pacify gcc-4.3, which suggests explicit braces here
to avoid an ambiguous else.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71924 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-16 03:28:54 +00:00
Jakob Stoklund Olesen
48872e0d84 Pass to verify generated machine code.
The following is checked:

* Operand counts: All explicit operands must be present.

* Register classes: All physical and virtual register operands must be
  compatible with the register class required by the instruction descriptor.

* Register live intervals: Registers must be defined only once, and must be
  defined before use.

The machine code verifier is enabled with the command-line option
'-verify-machineinstrs', or by defining the environment variable
LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the
verifier errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71918 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-16 00:33:53 +00:00