Evan Cheng
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b46aaa3874
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Fix a regression from 76124. Thumb1 instructions default to S bit being true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76374 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-07-19 19:16:46 +00:00 |
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Anton Korobeynikov
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b8e9ac834a
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Emit cross regclass register moves for thumb2.
Minor code duplication cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-07-16 23:26:06 +00:00 |
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Evan Cheng
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ab33150445
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Move isPredicated from .cpp to .h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75217 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-07-10 01:38:27 +00:00 |
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David Goodwin
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77521f5232
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Generalize opcode selection in ARMBaseRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-07-08 20:28:28 +00:00 |
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David Goodwin
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334c26473b
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Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-07-08 16:09:28 +00:00 |
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