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21349 Commits

Author SHA1 Message Date
James Molloy
873fd5f753 Improve generated code for extending loads and some trunc stores on ARM. 
Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150956 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-20 09:24:05 +00:00
Ahmed Charles
b0934ab7d8 Remove dead code. Improve llvm_unreachable text. Simplify some control flow. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 11:37:01 +00:00
Craig Topper
1bf724b28b Remove some unneeded includes and fix ordering in X86ISelLowering.cpp. Remove unneeded 'using namespace'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150916 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 07:15:48 +00:00
Craig Topper
dd637ae0c3 Unify all shuffle mask checking functions take a mask and VT instead of VectorShuffleSDNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150913 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 05:41:45 +00:00
Craig Topper
5aaffa8470 Make a bunch of X86ISelLowering shuffle functions static now that they are no longer needed by isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150908 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 02:53:47 +00:00
Jia Liu
9ad012a29c comment fix ARM.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150904 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 02:04:03 +00:00
Jia Liu
44de83a7f6 some comment fix for X86 and ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150902 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 02:03:36 +00:00
Craig Topper
28a713b20a Add vmfunc instruction to X86 assembler and disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 01:39:49 +00:00
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-18 12:03:15 +00:00
Craig Topper
a771330366 Add X86InstrSVM.td that I forgot to add in r150873. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150874 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-18 08:34:12 +00:00
Craig Topper
9e3d0b3351 Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-18 08:19:49 +00:00
Jakob Stoklund Olesen
2420b558de Handle regmask operands in ARMInstrInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150833 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 19:23:15 +00:00
Jakob Stoklund Olesen
8c3b87cf19 Fix ARMBaseInstrInfo::getInstrLatency for calls. 
Calls always clobber CPSR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150831 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 19:07:59 +00:00
Jia Liu
c5707112e7 remove Emacs-tag form .cpp files in Mips Backend, and fix some typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150805 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 08:55:11 +00:00
Craig Topper
6e94e68b75 Remove the last of the old vector_shuffle patterns from X86 isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150795 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 07:02:34 +00:00
Akira Hatanaka
38bdc5762f Do not promote i32 arguments to i64. This was causing unnecessary sign extension 
instructions to be emitted.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150782 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 02:20:26 +00:00
Jia Liu
8f5e8c1cd6 add Emacs tag and fix some comment error in file headers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150775 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 01:23:50 +00:00
Chad Rosier
b8703fe265 [fast-isel] Add support for returning non-legal types with no sign- or zero- 
entend flag.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150774 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 01:21:28 +00:00
Lang Hames
c2e08db4e5 Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE bail on reserved registers. This *should* be safe as of r150786. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150769 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 00:27:16 +00:00
Akira Hatanaka
178d870795 Remove comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150739 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-16 22:52:29 +00:00
Chad Rosier
a69feb0f33 Remove unnecessary assignment to temporary, ResultReg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150737 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-16 22:45:33 +00:00
Jakob Stoklund Olesen
8b0a3f2df9 Remove the YMM_HI_6_15 hack. 
Call clobbers are now represented with register mask operands.  The
regmask can easily represent the fact that xmm6 is call-preserved while
ymm6 isn't.  This is automatically computed by TableGen from the
CalleeSavedRegs containing xmm6.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150709 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-16 17:56:06 +00:00
Jakob Stoklund Olesen
527a08b253 Use the same CALL instructions for Windows as for everything else. 
The different calling conventions and call-preserved registers are
represented with regmask operands that are added dynamically.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150708 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-16 17:56:02 +00:00
Akira Hatanaka
e3186774f3 Remove trailing whitespace. Add newline. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150706 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-16 17:48:20 +00:00
Lang Hames
1834df8384 Oop - r150653 + r150654 broke one of my test cases. Backing out for now... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150655 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-16 02:32:10 +00:00
Lang Hames
afae28b1c6 FPSCR shouldn't be reserved. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150654 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-16 02:28:14 +00:00
Jakob Stoklund Olesen
8bcde2aa66 Enable register mask operands for x86 calls. 
Call instructions no longer have a list of 43 call-clobbered registers.
Instead, they get a single register mask operand with a bit vector of
call-preserved registers.

This saves a lot of memory, 42 x 32 bytes = 1344 bytes per call
instruction, and it speeds up building call instructions because those
43 imp-def operands no longer need to be added to use-def lists. (And
removed and shifted and re-added for every explicit call operand).

Passes like LiveVariables, LiveIntervals, RAGreedy, PEI, and
BranchFolding are significantly faster because they can deal with call
clobbers in bulk.

Overall, clang -O2 is between 0% and 8% faster, uniformly distributed
depending on call density in the compiled code.  Debug builds using
clang -O0 are 0% - 3% faster.

I have verified that this patch doesn't change the assembly generated
for the LLVM nightly test suite when building with -disable-copyprop
and -disable-branch-fold.

Branch folding behaves slightly differently in a few cases because call
instructions have different hash values now.

Copy propagation flushes its data structures when it crosses a register
mask operand. This causes it to leave a few dead copies behind, on the
order of 20 instruction across the entire nightly test suite, including
SPEC. Fixing this properly would require the pass to use different data
structures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150638 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-16 00:02:50 +00:00
Sirish Pande
ab7955b9ce Optimize redundant sign extends and negation of predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150606 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-15 18:52:27 +00:00
Eric Christopher
2a4bc1e703 Revert "Replacing HexagonOptimizeSZExtends with HexagonPeephole." 
This reverts commit 1656806a944bbd23e98c6e578810fe02495ab741.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150605 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-15 18:34:25 +00:00
Eric Christopher
eddd6abdde Revert "Optimize redundant sign extends and negation of predicates" 
as it's breaking the build.

This reverts commit 11241abca5.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150604 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-15 18:32:25 +00:00
Sirish Pande
a997b3e51a Replacing HexagonOptimizeSZExtends with HexagonPeephole. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150603 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-15 18:31:35 +00:00
Sirish Pande
11241abca5 Optimize redundant sign extends and negation of predicates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150601 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-15 18:22:18 +00:00
Chad Rosier
40d552e0be Add braces to if clause to make symmetric with associate else clause. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150591 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-15 17:36:21 +00:00
Bill Wendling
4a1ff2fb3e Strip the pointer casts from the constants here. 
The c'tor list is stored as a list of 'void ()*'s, so all of the functions are
bitcast to that. However, the dyn_cast doesn't automagically look through
bitcasts. Do that for it.
<rdar://problem/10813350>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150572 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-15 09:14:08 +00:00
Andrew Trick
5e108eeeef Added TargetPassConfig::disablePass/substitutePass as a general mechanism to override specific passes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150562 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-15 03:21:47 +00:00
Chad Rosier
15b4497333 Use a temporary variable, rather then a series of redundant calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150538 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-15 00:36:26 +00:00
Pete Cooper
9989a63818 Stop custom lowering forr x86 DEC64m from happening if the load in the lowered sequence has more than 1 user 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150537 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-15 00:33:37 +00:00
Chad Rosier
92fd017364 Use a temporary variable, rather then a series of redundant calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150536 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-15 00:23:55 +00:00
Chad Rosier
5793a6586d Remove unnecessary assignment to temporary, ResultReg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150520 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-14 22:29:48 +00:00
Craig Topper
233a64846e Move old movl vector_shuffle patterns. Not needed anymore since vector_shuffles shouldn't reach isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150462 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-14 08:14:53 +00:00
Lang Hames
1a4cb1caf0 Third time's the charm...? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150447 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-14 00:34:30 +00:00
Lang Hames
6b0e9d97fa Unswap swap operands, partially reducing confusion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150444 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-14 00:17:12 +00:00
Bill Wendling
bdf9db6f49 Don't reserve the R0 and R1 registers here. We don't use these registers, and 
marking them as "live-in" into a BB ruins some invariants that the back-end
tries to maintain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150437 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 23:47:16 +00:00
Lang Hames
2cc494b963 Make operands for VSWP read-modify-write. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150433 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 23:37:19 +00:00
Craig Topper
7505626acd Still more vector_shuffle pattern removal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150365 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 07:23:41 +00:00
Ahmed Charles
b83a67e1e3 Fix various issues (or do cleanups) found by enabling certain MSVC warnings. 
- Use unsigned literals when the desired result is unsigned. This mostly allows unsigned/signed mismatch warnings to be less noisy even if they aren't on by default.
- Remove misplaced llvm_unreachable.
- Add static to a declaration of a function on MSVC x86 only.
- Change some instances of calling a static function through a variable to simply calling that function while removing the unused variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150364 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 06:30:56 +00:00
Craig Topper
4eaca023dc Remove more vector_shuffle patterns for unpack. These should be target specific nodes when they get to isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150363 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 05:48:49 +00:00
Craig Topper
3b17bf9a7c Recommit r150328. Previous test failures should be fixed by r150360. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150362 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 05:10:10 +00:00
Craig Topper
2dcd718c13 Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150360 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 04:30:38 +00:00
NAKAMURA Takumi
7f42e9886e Revert r150328, "Remove more vector_shuffle patterns." 
It caused 3 failures on pre-penryn and non-x86(generic) hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150357 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 00:10:15 +00:00